Lauterbach has announced the addition of support for SoC-600 to their TRACE32 debug tool. The Arm Debug Interface (ADIv6), more commonly referred to as SoC-600, is the next generation of processor and architecture independent debug interface specification from Arm. Although initially available on Armv8 devices, it can be implemented on any architecture.
There are some compelling reasons for silicon designers to adopt the SoC-600 standard, according to Lauterbach. It is completely processor and architecture agnostic; it can be adapted to fit where-ever there is a requirement for a scalable, comprehensive debug interface. It provides a new standard and is likely to already be implemented by many tool vendors, including Lauterbach.
Traditional debug interfaces like JTAG form only a small part of the SoC-600 story and these have been moved into a dedicated link layer. This allows for debug connections from almost any source and some of those being considered within the industry include: JTAG-DP, SW-DP, SWJ-DP, PCIe, USB (MIPI SneakPeek), UDP/TCP/IP, self-hosted debug using on-chip resources, GTL and UItraSoC PAMs. The mantra has become: “If you can connect to a device, you can run a debug session over that connection.”
The memory interface has been radically redesigned and it now supports multiple memory access ports which are independent of the main debug tool link. These can now interface to every memory bus on the target system, not just those that are present internally within a CPU/SoC. Memory ports can be nested to form a hierarchical access tree and the TRACE32 configuration capabilities have been extended so that users can describe to the debugger how the memory ports are nested and connected.
Once this initial setup has been performed, accessing any memory becomes a simple task with little difference from the standard debug interface. The memory access ports were designed to be independent of the interface link allowing for a much greater flexibility in system design.
Lauterbach | www.lauterbach.com