Product News

Low-Jitter 1.25-GSPS Clock Optimizes JESD204B Serial Interface Functionality in GSPS Data Converter Applications

Analog Devices recently introduced the AD9528 JESD204B clock and SYSREF generator defined to support the clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs, defense electronics systems, RF test instrumentation, and more. According to Analog devices, the JESD204B interface was developed “to address high-data rate system design needs, and the AD9528 clock device contains functions that support and enhance the unique capabilities of that interface standard.”

The AD9528 provides a low-power, multi-output, clock distribution function with low-jitter performance, along with an on-chip, two-stage PLL and VCO. The on-chip VCO tunes from 3.6 to 4.0 GHz.

When connected to a recovered system reference clock and a VCXO, the AD9528 generates 12 low-noise outputs with a range of 1 to 400 MHz and two high-speed outputs at up to 1.25 GHz. The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase-select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming from the VCO output. The SYSREF signals each have additional phase offset capability making it easy to dial-in the optimal arrival time at each target device.

The AD9528 can be designed into wideband RF data acquisition applications with ADI’s AD9680 dual-channel, 14-bit, 1.0-GSPS JESD204B A/D converter.

The AD9528BCPZ costs $8.25 in 1,000-piece quantities. The evaluation board costs $190.


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