NXP Semiconductors has launched the LPC5500 which the company claims as the industry’s first microcontroller platform with single- and dual-core Arm Cortex-M33 and Arm TrustZone technology. Built on a low-power 40 nm embedded flash process, the LPC5500 MCU achieves 32uA/MHz efficiency at up to 100 MHz core clock frequency. It also provides dual-core Cortex-M33 capability with additional tightly coupled accelerators for signal processing and cryptography, and up to 640 KB flash and 320 KB on-chip SRAM for advanced edge applications.
LPC55S69 integrates a 16-bit Successive Approximation ADC (SAR ADC) with differential pair mode; a rich set of peripherals for system expansion, including, 50 MHz high-speed SPI, a High-Speed USB with integrated physical transceiver, eight flexible communication interfaces; and dual SDIO interfaces for concurrent Wi-Fi connection and external data logging. NXP’s autonomous programmable logic unit for offloading and execution of user defined tasks provides enhanced real-time parallelism.
One of the key features of the Cortex-M33 is its dedicated co-processor interface that extends the processing capability of the CPU by allowing efficient integration of tightly-coupled co-processors, while maintaining full ecosystem and toolchain compatibility. NXP has utilized this capability to implement a co-processor for accelerating key ML and DSP functions, such as, convolution, correlation, matrix operations, transfer functions and filtering; enhancing performance by as much as 10x compared to executing on Cortex-M33. The co-processor further leverages the popular CMSIS-DSP library calls (API) to simplify customer code portability.
Integrated benchmark security features: secure boot with immutable hardware ‘root-of-trust,’ SRAM PUF based unique key storage, certificate based secure debug authentication, AES-256 & SHA2-256 acceleration, and DICE security standard implementation for secure cloud-to-edge communication. The public key infrastructure (PKI), or asymmetric cryptography, is further accelerated by the dedicated asymmetric accelerator for ECC and RSA algorithms.
The LPC5500 MCU series features pin-, software- and peripheral compatibility across seven distinct families, with varying levels of functionality. The lead device family is enabled with LPC55S69-EVK, an evaluation board supported by NXP’s MCUXpresso Integrated Development Environment (IDE) and comprehensive software development kit which includes peripheral drivers, security and connectivity middleware, Amazon FreeRTOS based demos, and Arm TrustZone based security examples. Partner tools from Arm Keil MDK, IAR Embedded Workbench, Segger and others have been enabled to support LPC55S69-EVK.
NXP is sampling LPC55S69 development boards and 100-pin LQFP packages, with associated MCUXpresso based software development kit, through NXP field sales representatives. Direct to customer sampling on NXP eCommerce platform is expected by end of 2018. Volume production commences in Q1-2019. Devices within the LPC55S6x family are starting at a per unit price of $1.99 for 256K B flash and $2.49 for 640 KB flash, in 10,000-unit quantities.
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