Cypress Semiconductor has announced the inclusion of Cypress’ high-bandwidth HyperBus 8-bit serial memory interface into the new eXpanded SPI (xSPI) electrical interface standard from the JEDEC Solid State Technology Association. The xSPI standard defines requirements for the compatibility of high-performance x8 serial interfaces, enabling controller and chipset manufacturers to design a universal memory controller. The inclusion of the HyperBus interface in the JEDEC xSPI standard simplifies designing in HyperBus-based memories and provides more flexibility to system designers to implement instant-on functionality in automotive, industrial and IoT applications.
According to Cypress, the company was the first NOR flash memory supplier to identify the market requirement for a high-speed, 8-bit bus and introduced the HyperBus interface in 2014, ushering in a new class of high-performance NOR flash and RAM solutions that enable instant-on functionality for autonomous driving and industry 4.0 applications. Cypress’ HyperBus-based memories include high-density HyperFlash NOR Flash devices with the bandwidth required for the highest-performance embedded systems and high-speed HyperRAM self-refresh DRAM devices for systems requiring expanded scratchpad memory.
The xSPI standard defines requirements for the compatibility of high-performance x8 serial interfaces, including read and write commands, electrical characteristics, signaling protocols for command and data transfers, and a standard pin-out in a BGA footprint.
The 12-pin Cypress HyperBus interface consists of an 8-pin address/data bus, a differential clock (2 signals), one chip select and a read data strobe for the controller, reducing the overall cost of a system. Memories based on the interface enable faster systems with quicker response times and rich user experiences. The HyperBus interface enables a wide range of high-performance applications, such as automotive instrument clusters, infotainment and navigation systems and factory automation systems.
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