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Dual-Core, Runtime-Reconfigurable Processor for Low-Power Applications

Imsys has developed a dual-core, runtime-reconfigurable processor that can run at 350 MHz with an active power consumption of 19.7 µW/MHz using one core. Intended for low-power applications, 97% of the processor’s transistors are used in memory blocks. The cores share memories and a five-port grid network router (NoC). Memory management is handled by microcode, and memory is closely integrated with the processor without the need for an ordinary cache controller. The active consumption of each core—executing from RAM, including its consumption there—is 6.9 mW at 350 MHz.

Imsys’s processor is suitable for sensor nodes powered by energy harvesting in the Internet of Things (IoT), as well as in many-core chips for microservers and robotics. Microcode, as opposed to logic gates, is compact and energy efficient. Imsys uses extensive microprogramming to accomplish a rich set of instructions, thereby reducing the number of cycles needed without energy inefficient speculative activity and duplicated hardware logic. Each core has two instruction sets, one of which executes Java and Python directly from the dense JVM bytecode representation. C code is compiled to the other set with unparalleled density. Internal microcode is used for computationally intensive standard routines, such as crypto algorithms, which would otherwise be assembly coded library routines or even special hardware blocks. Optimizing CPU intensive tasks by microcode can reduce execution time and energy consumption of by more than an order of magnitude compared to C code.

The rich instruction set optimized for the compiler reduces the memory needed for software. And just like the microcoded algorithms, it reduces the number of clock cycles needed for execution. This platform has a certified JVM and uses an RTOS kernel certified to ISO 26262 safety standard for automotive applications. The development tools will be enhanced with the support enabled by the LLVM infrastructure. A new instruction set optimized for an LLVM backend has been developed and is being implemented in the coming hardware generation.

Source: Imsys

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Dual-Core, Runtime-Reconfigurable Processor for Low-Power Applica…

by Circuit Cellar Staff time to read: 1 min