Cypress Semiconductor Corp. has announced a new high-performance programmable clock generator family that’s intended to simplify the design of consumer and networking systems. The new CY27410 4-PLL (phase-locked loop) clock generator can generate up to 12 programmable output frequencies on a single chip with superior jitter performance. The clock reduces both board space and BOM costs by consolidating system components to provide a flexible, low-cost solution.
With support for frequencies up to 700 MHz and RMS phase jitter of 0.7 ps, the CY27410 family supports reference clocks for PCIe 1.0/2.0/3.0, SATA1.0/2.0, 10GbE, and USB1.0/2.0/3.0 peripherals. The devices support on-board programming using I2C interface, adding to design flexibility. They can also store up to eight different configuration settings that are selectable using external digital control pins. The family supports 12 single-ended clock outputs, as well as eight differential output pairs that can be configured as HCSL, LVPECL, LVDS, CML, or LVCMOS outputs. The devices also integrate a unique combination of value-added features that simplify design, including VCXO, glitch-free outputs, EMI-reduction, configurability as a zero or nonzero delay buffer, early/late clocks and PLL cascading.
The CY27410 clocks come with the CY3679 evaluation kit and CyClockWizard 2.0 programming software to help designers create their desired frequencies and to easily check device performance.
The CY27410 clock generators are currently sampling. Production expected in Q2 2015. The devices are available in a 48-pin QFN package.
Source: Cypress Semiconductor
Circuit Cellar's editorial team comprises professional engineers, technical editors, and digital media specialists. You can reach the Editorial Department at email@example.com, @circuitcellar, and facebook.com/circuitcellar