As part of its Cortus IC Design Service offering, Cortus has announced the general availability of a complete range of RISC-V processors. These are now available for design-in in customer ASIC designs implemented by the experienced teams at Cortus. A wide range of application needs are covered by the 6 processor cores.
The range starts with a low gate count, very low power 32 bit CPU core—the APS1V (RV32EMC). A more powerful, but equally low power CPU, the APS3V (RV32IMC) comes next. If a multi-core solution is necessary the APS5V (RV32IMAC) is available. If floating point is needed then the single precision FPS6V (RV32IMACF) can be used or the FPS8V (RV32GC) for double precision calculations. The last member of the family is a high performance 64-bit processor with double precision floating point and MMU: the FPS69V (RV64GC). These processors have already been implemented in customer projects in the aerospace, satellite, industrial and automotive sectors. A complete development ecosystem is available, including graphical environment, compiler, debugger real time operating systems and tools. Billions of chips containing Cortus IP (including processor IP) have been manufactured based on the successful Cortus Ecosystem.
As with past workshops, this event will bring together the RISC-V community to share RISC-V activities underway around the globe, and build consensus on the future evolution of the instruction set architecture. Experience two days of presentations, keynotes, poster sessions, demos, networking and parties.
SiFive has launched the industry’s first Linux-capable RISC-V based processor SoC. The company demonstrated the first real-world use of the HiFive Unleashed board featuring the Freedom U540 SoC, based on its U54-MC Core IP, at the FOSDEM open source developer conference.
During the session, SiFive provided updates on the RISC-V Linux effort, surprising attendees with an announcement that the presentation had been run on the HiFive Unleashed development board. With the availability of the HiFive Unleashed board and Freedom U540 SoC, SiFive has brought to market the first multicore RISC-V chip designed for commercialization, and now offers the industry’s widest array of RISC-V based Core IP.
With the Freedom U540, the first RISC-V based, 64-bit 4+1 multicore SoC with support for full featured operating systems such as Linux, the HiFive Unleashed development board will greatly spur open-source software development. The underlying CPU, the U54-MC Core IP, is ideal for applications that need full operating system support such as artificial intelligence, machine learning, networking, gateways and smart IoT devices.
The company also announced its first hackathon, which will be held during the Embedded Linux Conference, March 12 to 14 in Portland, OR. The hackathon will enable registered SiFive Developers to be among the first test out SiFive’s HiFive Unleashed board featuring the U540 SoC.
Freedom U540 processor specs include:
4+1 Multi-Core Coherent Configuration, up to 1.5 GHz
4x U54 RV64GC Application Cores with Sv39 Virtual Memory Support
1x E51 RV64IMAC Management Core
Coherent 2MB L2 Cache
64-bit DDR4 with ECC
1x Gigabit Ethernet
Built in 28nm process technology
The HiFive Unleased development board specs include:
SiFive Freedom U540 SoC
8GB DDR4 with ECC for serious application development
Gigabit Ethernet Port
32MB Quad SPI Flash
MicroSD Card for removable storage
FMC Connector for future expansion with add-in cards
Developers can purchase the HiFive Unleashed development board here. A limited batch of early access boards will ship in late March 2018, with a wider release in June. For more information or to register for the hackathon, visit www.sifive.com/products/hifive-unleashed/.
During his busy sabbatical, Krste Asanovic took time to share his thoughts on developments n the world of processors and the open sourcing of processor architecture.
Moore’s Law and the Chip Industry’s Perfect Storm
By Wisse Hettinga
With the end of Moore’s Law in sight and a silicon manufacturing world that is struggling to protect their investments, the RISC-V foundation is throwing its nets out on the other side of the boat. How? By creating an opensource platform for future new silicon development.
“There is a lot of friction in the market,” Asanovic explains. Being a professor at Berkeley University in Computer Architecture, he knows what he is talking about. “With RISC-V we want to reduce this friction in the industry. One of the problems is the IP protection and business involvement in the industry. With SiFive you don’t have to deal with complicated contracts. Users can just come and take the material that’s all published and open source and use it in their future chip design.”
Krste Asanovic is a SiFive founder and Professor of Computer Architecture at Berkeley University.
“The Barcelona Computer Centre is showing great interest in what we are doing with RISC-V. And the UPC computer architecture department is one of the strongest architecture group in Europe. Here—and also in the rest of Europe—there is a lot of interest in RISC-V for research projects and also for possible industrial use,” says Asanovic.
HETTINGA: Can you explain what RISC-V is?
ASANOVIC: RISC-V is an instruction set architecture (ISA). An ISA is what you use to encode software to run on hardware. In the industry there are common standards like the x86 from Intel and AMD. There’s also the ARM architecture we all know from our mobile phones and tablets. RISC-V uses different encoding which is meant to be free and open so that everyone can use without paying license fee—which is unlike the existing proprietary standards. Our goal is to have an open standard anybody can use.
HETTINGA: And what’s the level of interest from the market today for RISC-V?
ASANOVIC: If you look at the market, the x86 architecture is dominant in desktops and servers. ARM is dominant in mobile phones and tablets—and it will probably remain so. But what is interesting is that there are always new markets coming along: IoT (Internet of Things) and automotive are big markets. At the high-end of the market we see storage controllers and machine learning accelerators. These are all new greenfield areas where people are looking at new chip designs. They don’t have a large legacy of software and they are open to a new instruction set—particularly ones that are free of all sorts of legal and financial strings and give them flexibility to bring new things into the controller architecture.
HETTINGA: Give us a little history of RISC and of RISC versus CISC.
ASANOVIC: The RISC architecture goes a long way back and it’s still alive. I trace the roots of RISC way back to Seymour Cray’s early machines—like the CDC 6600—from 1964. RISC machines are register rich and have a load/store architecture. They have a lot of general registers and all operations are between registers except for the memory operations. That style of machine has remained popular for over 50 years and has outlived Moore’s Law.
Meanwhile, CISC has also been around for some time. CISC was a product of the time before integrated silicon started replacing the vacuum tubes and magnetic core memory systems. It is interesting to see that over the last couple decades there has been very little new development in the CISC architecture arena. I think everyone will agree that if you start from scratch, CISC is not a great idea.
RISC-V follows the heritage of the earlier RISC processor designs developed at Berkeley University. “RISC-V” means it is the fifth generation. We started on the project in 2010 and we were tired of using commercial ISAs for research. They were sometimes too complicated for what we wanted to do, and with the IP entanglements it is very difficult to share that research with others.
As academics, we like to share our work with others. We realized we did not want to invest in proprietary architectures. Also, a lot of commercial products are not that good. There was a quality problem and we thought we could do a lot better.
The response was overwhelming and very quickly it was getting too big for Berkeley and we started the RISC-V foundation. The goal of the foundation is to maintain the RISC-V ISA standard and we have grown to over 60 companies—including the biggest names like Qualcomm, Samsung, Microsoft, Western Digital, IBM and Google.
HETTINGA: From there, how did RISC-V lead to the creation of the SiFive organization?
ASANOVIC: At Berkeley we’ve done a great deal of research into RISC architecture, involving teams and activities. They did implementations, ported the compilers and Linux and got other operating systems up and running. Having a ‘critical mass’ of graduate students working on this project allowed people from outside to pick it up and do real work with it. It started off as an idea to have a consultancy activity around RISC-V. The co-founders—Andrew Waterman and Yunsup Lee—soon realized the opportunity and that’s why I also decided to get involved as a founder.
HETTINGA: This seems to be a very significant time in the semiconductor industry. How would you characterize where we’re at today?
ASANOVIC: The semiconductor industry is in this perfect storm where we see that Moore’s Law is ending and that new technologies and developments are getting more and more expensive. There are fewer and fewer companies capable of pulling off a new design and making money out of it. At the same time there is a growth in demand for custom chips. Everybody is talking about the Internet of Things and all those devices will need a processor—and that cannot be the same processor for all solutions. There will be a growth in silicon products, but that growth will be in many fragmented markets. The old semiconductor business model—having one design and selling many millions of it— doesn’t work anymore. That has worked with the traditional computer and mobile phone markets, but the future will see perhaps hundreds of designs in lower volumes.
With SiFive we try to figure out how this works. The traditional users of the chips are now becoming the new manufacturers. Google. Microsoft, Amazon and a lot of other companies will design and make their own chips—not to sell to others, but to use them in their own products. It will allow them to add capabilities that are not available in standard off-the-shelf chips.
Our mission is to find out if we can help smaller companies and startups to do custom silicon design and invent new products with new capabilities. We believe there is a lot of untapped innovation there. But the problem is the barrier to enter custom silicon design is too high and those great ideas do not become a product. Solving that problem is the goal of SiFive.
SiFive’s RISC-V Arduino board makes it easy for small companies to get started with new designs.
HETTINGA: Tell us about SiFive’s RISC-V Arduino reference design board.
ASANOVIC: Our business model is to do quick developments of new chipsets and help the client to get into production at very low costs. To enable that, we made an Arduino board (at the time of the interview the new Arduino Cinque was introduced / WH) that runs very fast. And by putting it into the Arduino format a lot of small design companies will see it and can use it for new designs. The interesting thing about this product is that it will take the focus from the board to the chip level. Not only the board is open source but the chip design is too. That can open up completely new perspectives for makers, start-up companies and medium-sized businesses. All the design files of the chip are open source are on Github. This is unique in the semiconductor business. With SiFive we want to get rid of the friction in the industry. We don’t have a costly structure with NDAs and lawyers. A lower cost structure will also mean lower costs for our clients. You can come and take the designs as they are and use them.
It is truly a thrill and an honor for me to be joining the Circuit Cellar team as the magazine’s new Editor-in-Chief. And in this—my first editorial in my new role—I want to seize the opportunity to talk about Circuit Cellar. A lot of factors attracted me to this publication. But in a nutshell its position in the marketplace is compelling. It intersects with two converging trends happening in technology today.
First, there’s the phenomenon of the rich set of tools, chips, and information resources available today. They put more power into the hands of makers and electronics DIY experts than ever before. You’ve got hardware such as Arduino and Raspberry Pi. Open source software ranging from Linux to Eclipse make integrating and developing software easier than ever. And porting back and forth between open source software and commercial embedded software is no longer prohibitive now that commercial software vendors are in a “join them, not beat them” phase of their thinking. Easy access has even reached processors thanks to the emergence of RISC-V for example (click here for more). Meanwhile, powerful FPGA chips enable developers to use one chip where an entire board or box was previously required.
The second big trend is how system-level chip technologies—like SoC-style processors and the FPGAs I just mentioned—are enabling some of the most game-changing applications driving today’s markets: including commercial drones, driverless cars, Internet-of-Things (IoT), robotics, mobile devices and more. This means that exciting and interesting new markets are attracting not just big corporations looking for high volume play, but also small start-up vendors looking to find their own niche within those market areas. And there are a lot of compelling opportunities in those spaces. Ideas that start as small embedded systems projects can—and are—blossoming into lucrative new enterprises.
What’s so exciting is that Circuit Cellar readers are at the center of both those two trends. There’s a particular character this magazine has that separates it from other technology magazines. There are a variety of long-established publications that cover electronics and whose stated missions are to serve engineers. I’ve worked for some of them, and they all have their strengths. But you can tell just by looking at the features and columns of Circuit Cellar that we don’t hold back or curtail our stories when it comes to technical depth. We get right down to the bits and bytes and lines code. Our readers are engineers and academics who want to know not only the rich details of a microcontroller’s on-board peripherals, but also how other like-minded geeks applied that technology to their DIY or commercial project. They want to know if the DC-DC converter they are considering has a wide enough input voltage to serve their needs.
Another cool thing for me about Circuit Cellar is the magazine’s origin story. Back when I was in high school and in my early days studying Computer Science in college, Steve Ciarcia had a popular column called Circuit Cellar in BYTE magazine. I was a huge fan of BYTE. I would take my issue and bring it to a coffee shop and read it intently. (Mind you this was pre-Internet. Coffee shops didn’t have Wi-Fi.) What I appreciated most about BYTE was that it had far more technical depth than the likes of PC World and PC Computing. I felt like it was aimed at a person with a technical bent like myself. When Steve later went on to found this magazine—nearly 30 years ago—he gave it the Circuit Cellar name but he also maintained that unique level of technical depth that entices engineers.
With all that in mind, I plan to uphold the stature and legacy in the electronics industry that I and all of you have long admired about Circuit Cellar. We will work to continue being the Most Technical information resource for professional engineers, academics, and other electronics specialists world-wide. Meanwhile, you can look forward to expanded coverage of those exciting market-spaces I discussed earlier. Those new applications really exemplify how embedded computing technology is changing the world. Let’s have some fun.
SiFive recently introduced the Freedom family of system on a chip (SoC) platforms that are built around the open-source RISC-V instruction set architecture, which was developed by the company’s founders at the University of California, Berkeley.
Features and specs:
Freedom U500 Series: The Freedom Unleashed (U) family features a fully Linux-capable embedded application processor featuring the world’s most advanced, multi-core RISC-V CPUs, running at a speed of 1.6 GHz or higher with support for accelerators and cache coherency. Designed in TSMC 28 nm, the Freedom U500 platform is well suited for machine learning, storage, and networking applications. The platform also supports standard high-speed peripherals including PCIe 3.0, USB 3.0, Gigabit Ethernet, and DDR3/DDR4.
Freedom E300 Series: The Freedom Everywhere (E) family is designed for embedded microcontroller, IoT, and wearables markets. Designed in TSMC 180 nm and architected to have minimal area and power, the Freedom E300 platform features efficient RISC-V cores with support for RISC-V compressed instructions that have been shown to reduce code size by up to 30%.
Full FPGA models of each SoC are now available. Visit dev.sifive.com for more information.