NXP Semiconductors has announced a collaboration with Microsoft to deliver a new Microsoft Azure Sphere certified crossover applications processor, as an extension to NXP’s i.MX 8 high-performance applications processor series. The collaboration’s goal is to create a secure, ultra-efficient, intelligent embedded processor for edge nodes that seamlessly runs Azure Sphere’s security platform while also providing multi-core heterogeneous computing, rich graphics experience and low-power audio processing capabilities. Limited sampling of the product is planned to begin in Q4 2020.
Azure Sphere security platform is designed to create secure connected devices. As Azure Sphere-certified, this new processor will include the Microsoft Pluton security sub-system, run the Azure Sphere OS, and connect to the Azure Sphere Security Service that guards every Azure Sphere device by renewing security, identifying emerging threats, and brokering trust between device and cloud.
According to NXP, Dedicated engineering teams from each company will work together to build this new solution, which includes single and dual core versions of power-efficient Arm Cortex-A35, independent real-time domain with Cortex-M33 core, and an independent audio/video processing domain powered by high-performance HiFi4 DSP core. The goal is to address the needs of fast-growing Industrial IoT edge applications. The product will be built using Fully-Depleted Silicon-On-Insulator (FD-SOI) technology and will leverage heterogeneous processor architecture with independent power domains that has been perfected by successive designs of i.MX 8 applications processors covering automotive infotainment, streaming media and general-purpose consumer and industrial markets.
STMicroelectronics has teamed up with Virscient to help system designers build automotive solutions using ST’s Telemaco3P secure telematics and connectivity processors. Virscient offers support to ST customers in the development and delivery of advanced automotive applications based on the ST Modular Telematics Platform (MTP). MTP is a comprehensive development and demonstration platform incorporating ST’s Telemaco3P telematics and connectivity microprocessor.
MTP enables the rapid prototyping and development of smart-driving applications, including vehicle connectivity to back-end servers, road infrastructure, and other vehicles. Virscient brings a deep understanding of wireless connectivity technologies and protocols ideal for architecting connected-car systems that rely on technologies such as GNSS (Precise Positioning), LTE/cellular modems, V2X technologies, Wi-Fi, Bluetooth and Bluetooth Low Energy (BLE).
The Telemaco3P incorporates dual Arm Cortex-A7 processors with an embedded Hardware Security Module (HSM), an independent Arm Cortex-M3 subsystem, and a rich set of connectivity interfaces. With security at its core, and considerable flexibility in both hardware and software configurations, the Telemaco3P provides an excellent platform for connectivity within the vehicular environment.
ST’s Telemaco3P system-on-chip is designed as a solution for ensuring a secure connection between the vehicle and the Cloud. Its asymmetric multi-core architecture provides powerful application processors as well as an independent CAN control subsystem with optimized power management. Its ISO 26262 silicon design, its embedded Hardware Security Module, and automotive-grade qualification up to 105°C ambient temperature make it well suited for implementing a wide range of secure telematics applications supporting high-throughput wireless connectivity and over-the-air firmware upgrades.
First announced in February at Embedded World 2018, NXP Semiconductors has released its i.MX RT1060 Crossover processor, with the company claiming a mere ten months from concept to market launch.
The i.MX RT1060 is the latest addition to what NXP calls a crossover processor series and expands the i.MX RT series to three scalable families. The i.MX RT1060 doubles the On-Chip SRAM to 1 MB while keeping pin-to-pin compatibility with i.MX RT1050. This new series introduces additional features ideal for real-time applications such as High-Speed GPIO, CAN-FD, and synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the Arm Cortex-M7 core at 600 MHz.
This device is fully supported by NXP’s MCUXpresso Software and Tools, a comprehensive and cohesive set of free software development tools for Kinetis, LPC and i.MX RT microcontrollers. MCUXpresso SDK also includes project files for Keil MDK and IAR EWARM.
The i.MX RT crossover are designed to bridge the gap between high-performance and integration while minimizing costs to meet today’s need for high performance embedded processing at the edge node. According to NXP the series were designed to combine high performance MCU processing with the functionality of applications processors, at reduced costs, thereby enabling advanced computation and machine learning capabilities in millions of connected edge devices. The i.MX RT1060 is available now, and is priced at $3.48 (10,000s).
Vicor has announced the introduction of Power-on-Package modular current multipliers for high performance, high current, CPU/GPU/ASIC (“XPU”) processors. By freeing up XPU socket pins and eliminating losses associated with delivery of current from the motherboard to the XPU, Vicor’s Power-on-Package solution enables higher current delivery for maximum XPU performance.
In response to the ever-increasing demands of high performance applications–artificial intelligence, machine learning, big data mining—XPU operating currents have risen to hundreds of Amperes. Point-of-Load power architectures in which high current power delivery units are placed close to the XPU, mitigate power distribution losses on the motherboard but do nothing to lessen interconnect challenges between the XPU and the motherboard. With increasing XPU currents, the remaining short distance to the XPU—the “last inch”—consisting of motherboard conductors and interconnects within the XPU socket has become a limiting factor in XPU performance and total system efficiency.
Vicor’s new Power-on-Package Modular Current Multipliers (“MCMs”) fit within the XPU package to expand upon the efficiency, density, and bandwidth advantages of Vicor’s Factorized Power Architecture, already established in 48 V Direct-to-XPU motherboard applications by early adopters. As current multipliers, MCMs mounted on the XPU substrate under the XPU package lid, or outside of it, are driven at a fraction (around 1/64th) of the XPU current from an external Modular Current Driver (MCD). The MCD, located on the motherboard, drives MCMs and accurately regulates the XPU voltage with high bandwidth and low noise. The solution profiled today, consisting of two MCMs and one MCD, enables delivery of up to 320 A of continuous current to the XPU, with peak current capability of 640 A.
With MCMs mounted directly to the XPU substrate, the XPU current delivered by the MCMs does not traverse the XPU socket. And, because the MCD drives MCMs at a low current, power from the MCD can be efficiently routed to MCMs reducing interconnect losses by 10X even though 90% of the XPU pins typically required for power delivery are reclaimed for expanded I/O functionality. Additional benefits include a simplified motherboard design and a substantial reduction in the minimum bypass capacitance required to keep the XPU within its voltage limits.
Multiple MCMs may be operated in parallel for increased current capability. The small (32mm x 8mm x 2.75mm) package and low noise characteristics of the MCM make it suitable for co-packaging with noise-sensitive, high performance ASICs, GPUs and CPUs. Operating temperature range is -40°C to +125°C. These devices represent the first in a portfolio of Power-on-Package solutions scalable to various XPU needs.
During his busy sabbatical, Krste Asanovic took time to share his thoughts on developments n the world of processors and the open sourcing of processor architecture.
Moore’s Law and the Chip Industry’s Perfect Storm
By Wisse Hettinga
With the end of Moore’s Law in sight and a silicon manufacturing world that is struggling to protect their investments, the RISC-V foundation is throwing its nets out on the other side of the boat. How? By creating an opensource platform for future new silicon development.
“There is a lot of friction in the market,” Asanovic explains. Being a professor at Berkeley University in Computer Architecture, he knows what he is talking about. “With RISC-V we want to reduce this friction in the industry. One of the problems is the IP protection and business involvement in the industry. With SiFive you don’t have to deal with complicated contracts. Users can just come and take the material that’s all published and open source and use it in their future chip design.”
Krste Asanovic is a SiFive founder and Professor of Computer Architecture at Berkeley University.
“The Barcelona Computer Centre is showing great interest in what we are doing with RISC-V. And the UPC computer architecture department is one of the strongest architecture group in Europe. Here—and also in the rest of Europe—there is a lot of interest in RISC-V for research projects and also for possible industrial use,” says Asanovic.
HETTINGA: Can you explain what RISC-V is?
ASANOVIC: RISC-V is an instruction set architecture (ISA). An ISA is what you use to encode software to run on hardware. In the industry there are common standards like the x86 from Intel and AMD. There’s also the ARM architecture we all know from our mobile phones and tablets. RISC-V uses different encoding which is meant to be free and open so that everyone can use without paying license fee—which is unlike the existing proprietary standards. Our goal is to have an open standard anybody can use.
HETTINGA: And what’s the level of interest from the market today for RISC-V?
ASANOVIC: If you look at the market, the x86 architecture is dominant in desktops and servers. ARM is dominant in mobile phones and tablets—and it will probably remain so. But what is interesting is that there are always new markets coming along: IoT (Internet of Things) and automotive are big markets. At the high-end of the market we see storage controllers and machine learning accelerators. These are all new greenfield areas where people are looking at new chip designs. They don’t have a large legacy of software and they are open to a new instruction set—particularly ones that are free of all sorts of legal and financial strings and give them flexibility to bring new things into the controller architecture.
HETTINGA: Give us a little history of RISC and of RISC versus CISC.
ASANOVIC: The RISC architecture goes a long way back and it’s still alive. I trace the roots of RISC way back to Seymour Cray’s early machines—like the CDC 6600—from 1964. RISC machines are register rich and have a load/store architecture. They have a lot of general registers and all operations are between registers except for the memory operations. That style of machine has remained popular for over 50 years and has outlived Moore’s Law.
Meanwhile, CISC has also been around for some time. CISC was a product of the time before integrated silicon started replacing the vacuum tubes and magnetic core memory systems. It is interesting to see that over the last couple decades there has been very little new development in the CISC architecture arena. I think everyone will agree that if you start from scratch, CISC is not a great idea.
RISC-V follows the heritage of the earlier RISC processor designs developed at Berkeley University. “RISC-V” means it is the fifth generation. We started on the project in 2010 and we were tired of using commercial ISAs for research. They were sometimes too complicated for what we wanted to do, and with the IP entanglements it is very difficult to share that research with others.
As academics, we like to share our work with others. We realized we did not want to invest in proprietary architectures. Also, a lot of commercial products are not that good. There was a quality problem and we thought we could do a lot better.
The response was overwhelming and very quickly it was getting too big for Berkeley and we started the RISC-V foundation. The goal of the foundation is to maintain the RISC-V ISA standard and we have grown to over 60 companies—including the biggest names like Qualcomm, Samsung, Microsoft, Western Digital, IBM and Google.
HETTINGA: From there, how did RISC-V lead to the creation of the SiFive organization?
ASANOVIC: At Berkeley we’ve done a great deal of research into RISC architecture, involving teams and activities. They did implementations, ported the compilers and Linux and got other operating systems up and running. Having a ‘critical mass’ of graduate students working on this project allowed people from outside to pick it up and do real work with it. It started off as an idea to have a consultancy activity around RISC-V. The co-founders—Andrew Waterman and Yunsup Lee—soon realized the opportunity and that’s why I also decided to get involved as a founder.
HETTINGA: This seems to be a very significant time in the semiconductor industry. How would you characterize where we’re at today?
ASANOVIC: The semiconductor industry is in this perfect storm where we see that Moore’s Law is ending and that new technologies and developments are getting more and more expensive. There are fewer and fewer companies capable of pulling off a new design and making money out of it. At the same time there is a growth in demand for custom chips. Everybody is talking about the Internet of Things and all those devices will need a processor—and that cannot be the same processor for all solutions. There will be a growth in silicon products, but that growth will be in many fragmented markets. The old semiconductor business model—having one design and selling many millions of it— doesn’t work anymore. That has worked with the traditional computer and mobile phone markets, but the future will see perhaps hundreds of designs in lower volumes.
With SiFive we try to figure out how this works. The traditional users of the chips are now becoming the new manufacturers. Google. Microsoft, Amazon and a lot of other companies will design and make their own chips—not to sell to others, but to use them in their own products. It will allow them to add capabilities that are not available in standard off-the-shelf chips.
Our mission is to find out if we can help smaller companies and startups to do custom silicon design and invent new products with new capabilities. We believe there is a lot of untapped innovation there. But the problem is the barrier to enter custom silicon design is too high and those great ideas do not become a product. Solving that problem is the goal of SiFive.
SiFive’s RISC-V Arduino board makes it easy for small companies to get started with new designs.
HETTINGA: Tell us about SiFive’s RISC-V Arduino reference design board.
ASANOVIC: Our business model is to do quick developments of new chipsets and help the client to get into production at very low costs. To enable that, we made an Arduino board (at the time of the interview the new Arduino Cinque was introduced / WH) that runs very fast. And by putting it into the Arduino format a lot of small design companies will see it and can use it for new designs. The interesting thing about this product is that it will take the focus from the board to the chip level. Not only the board is open source but the chip design is too. That can open up completely new perspectives for makers, start-up companies and medium-sized businesses. All the design files of the chip are open source are on Github. This is unique in the semiconductor business. With SiFive we want to get rid of the friction in the industry. We don’t have a costly structure with NDAs and lawyers. A lower cost structure will also mean lower costs for our clients. You can come and take the designs as they are and use them.
The SBC35-CC405 series of multi-core embedded PCs includes on-board USB, gigabit Ethernet, and serial ports. These industrial computers are designed for rugged embedded applications requiring extended temperature operation and long-term availability.
The SBC35-CC405 series features the latest generation Intel Atom E3800 family of processors in an industry-standard 3.5” single-board computer (SBC) format COM Express carrier. A Type 6 COM Express module supporting a quad-, dual-, or single-core processor is used to integrate the computer. For networking and communications, the SBC35-CC405 includes two Intel I210 gigabit Ethernet controllers with IEEE 1588 timestamping and 10-/100-/1,000-Mbps multispeed operation. Four Type-A connectors support three USB 2.0 channels and one high-speed USB 3.0 channel. Two serial ports support RS-232/-422/-485 interface levels with clock options up to 20 Mbps in the RS-422/-485 mode and up to 1 Mbps in the RS-232 mode.
The SBC35-CC405 series also includes two MiniPCIe connectors and one IO60 connector to enable additional I/O expansion. Both MiniPCIe connectors support half-length and full-length cards with screw-down mounting for improved shock and vibration durability. One MiniPCIe connector also supports bootable mSATA solid-state disks while the other connector includes USB. The IO60 connector provides access to the I2C, SPI, PWM, and UART signals enabling a simple interface to sensors, data acquisition, and other low-speed I/O devices.
The SBC35-CC405 runs over a 10-to-50-VDC input power range and operates at temperatures from –40°C to 85°C. Enclosures, power supplies, and configuration services are also available.
Linux, Windows, and other x86 OSes can be booted from the CFast, mSATA, SATA, or USB interfaces, providing flexible data storage options. WinSystems provides drivers for Linux and Windows 7/8 as well as preconfigured embedded OSes.
The single-core SBC35-CC405 costs $499.
Elecronics engineer, entrepreneur, and author Jack Ganssle recently sent us information about his Finksburg, MD, workspace:
I’m in a very rural area and I value the quietness and the view out of the window over my desk. However, there are more farmers than engineers here so there’s not much of a high-tech community! I work out of the house and share an office with my wife, who handles all of my travel and administrative matters. My corner is both lab space and desk. Some of the equipment changes fairly rapidly as vendors send in gear for reviews and evaluation.
Ganssle’s desk is home to ever-changing equipment. His Agilent Technologies MSO-X-3054A mixed-signal oscilloscope is a mainstay.
The centerpiece, though, is my Agilent Technologies MSO-X-3054A mixed-signal oscilloscope. It’s 500 MHz, 4 GSps, and includes four analog channels and 16 digital channels, as well as a waveform generator and protocol analyzer. I capture a lot of oscilloscope traces for articles and talks, and the USB interface sure makes that easy. That’s pretty common on oscilloscopes, now, but being an old-timer I remember struggling with a Polaroid scope camera.
The oscilloscope’s waveform generator has somewhat slow (20-ns) rise time when making pulses, so the little circuit attached to it sharpens this to 700 ps, which is much more useful for my work. The photo shows a Siglent SDS1102CML oscilloscope on the bench that I’m currently evaluating. It’s amazing how much capability gets packed into these inexpensive instruments.
The place is actually packed with oscilloscopes and logic analyzers, but most are tucked away. I don’t know how many of those little USB oscilloscope/logic analyzers vendors have sent for reviews. I’m partial to bench instruments, but do like the fact that the USB instruments are typically quite cheap. Most have so-so analog performance but the digital sampling is generally great.
Only barely visible in the picture, under the bench there’s an oscilloscope from 1946 with a 2” CRT I got on eBay just for fun. It’s a piece of garbage with a very nonlinear timebase, but a lot of fun. The beam is aimed by moving a magnet around! Including the CRT there are only four tubes. Can you imagine making anything with just four transistors today?
The big signal generator is a Hewlett-Packward 8640B, one of the finest ever made with astonishing spectral purity and a 0.5-dB amplitude flatness across 0.5 MHz to 1 GHz. A couple of digital multimeters and a pair of power supplies are visible as well. The KORAD supply has a USB connection and a serviceable, if klunky, PC application that drives it. Sometimes an experiment needs a slowly changing voltage, which the KORAD manages pretty well.
They’re mostly packed away, but I have a ton of evaluation kits and development boards. A Xilinx MicroZed is shown on the bench. It’s is a very cool board that has a pair of Cortex-A9s plus FPGA fabric in a single chip.
I use IDEs and debuggers from, well, everyone: Microchip Technology, IAR Systems, Keil, Segger, you name it. These run on a variety of processors but, along with so many others, more and more I’m using Cortex-M series parts.
My usual lab work is either evaluating boards, products and instruments, or running experiments that turn into articles. It pains me to see so much engineering is done via superstition today. For example, people pick switch contact debounce times based on hearsay or smoke signals or something. Engineers need data, so I tested about 50 pairs of switches to determine what real bounce characteristics are. The results are on my website. Ditto for watchdog timers and other important issues embedded people deal with.