NXP and Microsoft Team Up for Energy-Efficient Edge Processor

NXP Semiconductors has announced a collaboration with Microsoft to deliver a new Microsoft Azure Sphere certified crossover applications processor, as an extension to NXP’s i.MX 8 high-performance applications processor series. The collaboration’s goal is to create a secure, ultra-efficient, intelligent embedded processor for edge nodes that seamlessly runs Azure Sphere’s security platform while also providing multi-core heterogeneous computing, rich graphics experience and low-power audio processing capabilities. Limited sampling of the product is planned to begin in Q4 2020.

Azure Sphere security platform is designed to create secure connected devices. As Azure Sphere-certified, this new processor will include the Microsoft Pluton security sub-system, run the Azure Sphere OS, and connect to the Azure Sphere Security Service that guards every Azure Sphere device by renewing security, identifying emerging threats, and brokering trust between device and cloud.

According to NXP, Dedicated engineering teams from each company will work together to build this new solution, which includes single and dual core versions of power-efficient Arm Cortex-A35, independent real-time domain with Cortex-M33 core, and an independent audio/video processing domain powered by high-performance HiFi4 DSP core. The goal is to address the needs of fast-growing Industrial IoT edge applications. The product will be built using Fully-Depleted Silicon-On-Insulator (FD-SOI) technology and will leverage heterogeneous processor architecture with independent power domains that has been perfected by successive designs of i.MX 8 applications processors covering automotive infotainment, streaming media and general-purpose consumer and industrial markets.

NXP Semiconductors | www.nxp.com

SST and UMC Qualify Flash Tech on 40-nm Process

Microchip Technology subsidiary Silicon Storage Technology (SST) and United Microelectronics Corporation (UMC) have announced the full qualification and availability of SST’s embedded SuperFlash non-volatile memory on UMC’s 40 nm CMOS platform. The 40-nm process features a more than 20 percent reduction in embedded Flash cell size and a 20- to 30-percent reduction in macro area over their 55-nm process.
The high endurance of embedded SuperFlash IP offers System on a Chip (SoC) customers extensive reliability and design flexibility combined with reduced power usage. SST’s SuperFlash non-volatile memory technology is qualified for a minimum of 100,000 cycles, underscoring the technology’s reliability. Ideal for edge computing in IoT devices, SST embedded SuperFlash technology features power benefits that derive from low-power standby and read operations, with core supply as low as 0.81 V. SuperFlash also secures applications with code maintained on chip, which is the first step in preventing illegal access through hardware and software attacks.

 

SST’s SuperFlash technology complements UMC’s embedded memory portfolio with high density and low-power IP. Combined with SST’s inherent technology reliability, UMC’s flexible capacity and high-yield maturity for its 55 nm and 40 nm platform provides foundry customers the manufacturing support needed to build a range of product applications.

To date, more than 80 billion units have shipped with SST’s embedded SuperFlash technology. SuperFlash technology is based on a proprietary split-gate Flash memory cell with the following capabilities:

  • Low-power program, erase and read operations
  • High performance with fast read access
  • Good scalability from 1 µm technology node to 28 nm technology node
  • High endurance cycling up to 500,000 cycles
  • Excellent data retention of over 20 years
  • Good performance at high temperature for automotive-grade applications
  • Immunity to Stress-Induced Leakage Current (SILC)

Microchip Technology | www.microchip.com

Silicon Storage Technology | www.sst.com