Integration Trend Leads PCB Design Tool Evolution

Comprehensive Solutions

After decades of evolving their PCB design tool suites, the leading tool vendors have the basics of PCB design nailed down. In recent years, these companies have continued to enhance their tools suites while also addressing a myriad of issues related to not just the PCB design itself, but the whole process surrounding it.

By Jeff Child, Editor-in-Chief

PCB design tools continue to evolve, as tool vendors scramble to keep pace with faster, highly integrated electronics. Automated, rules-based chip placement is getting more sophisticated and tools are addressing the broader picture of the PCB design process.

Over the last 12 months, PCB tool vendors have packed a smorgasbord of new features and capabilities into their PCB design software packages. The offerings include improved 3D design, design-phase signal integrity checks, advances in multi-board design functions, new design-for-manufacturing (DFM) features and more. Tool vendors are also tightening the links between IC, packaging and PCB design domains.

Improving DRCs

Exemplifying all those trends, In March, Mentor released the latest version of its Xpedition Enterprise design tool suite. According to Mentor, the VX.2.5 release offers new and improved features and functionality with an emphasis on ease of use and team productivity. The release includes advancements in design complexity management, improved reliability, quality, team collaboration and IP management. This includes new design rule checks (DRCs) for system design and NX 3D model support in EDM.

In Xpedition VX.2.5 new system design rule checks were created to review system integrity. Rule checks include cross-probing from integrity results to the specific item of interest can be enabled, verification that reference designators are unique in a single board and ensuring that the board connectors have been placed inside a board outline (Figure 1). Cable declarations are locked and names forwarded to the cable designer insuring that the required information is ready for “correct by construction” cable design.

Figure 1
In Xpedition, VX.2.5 new system design rule checks were created to review system integrity. Rule checks include cross-probing from integrity results to the specific item of interest.

Using the generic schematic symbol pin order for connectors doesn’t always achieve the desired results, says Mentor. In VX.2.5, users can now use the library symbol pin order column to easily edit pin numbers and the order. Pin orders can now be easily copied from an Excel spreadsheet and the connectors can be place by the pin numbers alpha-numeric value.

EDM in VX.2.5, along with Siemens NX, breaks down barriers with 3D model management. NX models can now be imported and exported in the EDM library cockpit ensuring tight integration, model integrity and accelerates collaboration. In VX.2.5, EDM Collaborate now enables users to view the net class and net topology information in the properties view. Whether you are viewing the schematic or layout, the information is available in properties and when selecting a net.

Routing Enhancements

Xpedition VX.2.5 also has a new capability called Semi Trunk routing that’s been added to Sketch Planning. This capability allows the user to create a Sketch plan that will only be routed on one end of the plan. By choosing the new command, Route Semi-Trunk, the Sketch plan will be optimized for the end opposite the Route to Dot, and then routed. This can help the user to pre-route interfaces that may still require placement or pin and gate swapping optimization. To complete optimization of an FPGA or ASIC and ensure the placement of the interface is complete, users can easily Reverse the Sketch plan to optimize the other end.

The new Xpedition version adds an advanced graphic orientation triad that enables users to quickly and easily control the 3D view. It also brings improvements to the online 3D DRC enabling users to identify critical interference issues quickly. From the hazard explorer users can select on interference issues and jump to their location to both view and resolve issues in the 3D environment.

Several additional electrical DRC checks are included in the new release. For signal integrity, a new reference rule covers traces vs. specific power nets. There is also a new Min/Max routed comp-to-comp length rule. Additionally, there is a novel Adjacent layer routing parallel coupling check as well as a new trace width check in BGA area vs. pin pad width. For power integrity, there is a new check for stitching via spacing. For ESD, there is a new check to ensure that components are aligned and finally, for Safety, there is a new rule that checks the distance between soldermask/silkscreen and any objects.

In version VX.2.5, the tool now integrates directly with HyperLynx advanced solvers for automatic board parasitic extraction. You can also select nets on the schematics, extract layout parasitic effects of selected nets, insert generated parasitic effects into simulation and evaluate the parasitic effects both with and without parasitics.

Marrying IC and PCB Design

One of the strengths of the PCB design tools from Cadence Design Systems is an ability to tie capabilities between the IC, packaging and PCB domains. One example is its Cadence’s OrbitIO interconnect designer (Figure 2). The tool revamps the cross-fabric planning and assessment process by unifying silicon, package and board data in a single canvas environment. This enables engineers to achieve the optimal balance of connectivity for performance, cost and manufacturability prior to implementation. That means fewer iterations and shorter development cycles.

Figure 2
Cadence’s PCB design tools feature an ability to tie capabilities between the IC, packaging and PCB domains. Its OrbitIO interconnect designer and Sigrity Technologies are two examples.

According to Cadence, the combination of growing functional integration at both the die and package level, combined with the latest high-performance interfaces, requires greater planning and coordination across all fabrics to achieve product performance objectives. That leaves little room for inefficient and error-prone methodologies.

The OrbitIO system planner provides an environment capable of uniting design content from various sources for the purpose of planning, then communicating the data back to their respective implementation tools for completion. It enables rapid exploration and evaluation of connectivity scenarios providing immediate feedback on the impact to adjacent devices and fabrics. Planning results and route plans are directly exchanged with package design resources whether it’s an internal group or outsourced assembly and test (OSAT) provider. As part of an overall Cadence co-design solution, OrbitIO interconnect designer can seamlessly exchange silicon, package and PCB data with their corresponding implementation tools.

Another way that Cadence provides solutions between different design domains is with its Sigrity family of signal integrity tools. The 2018 release of Sigrity features an upgraded interconnect modeling technology crafted to address latest trends on PCB and IC package design. With signal speeds climbing to 32 Gbps and faster, the need to strategically model PCBs and connectors as one structure is now required, says Cadence.

The new Cadence Sigrity 3D Workbench, included with the Sigrity PowerSI 3D EM Extraction Option (3DEM), enables system designers to import mechanical structures, such as cables and connectors, and merge them with the PCB so that critical 3D structures that cross from the board to the connector can be modeled and optimized as one structure. Updates to the PCB can be automatically back-annotated to the PCB layout tool.

DFM Partnerships

One the newest additions to the Cadence portfolio is its DesignTrue DFM technology. In September the company launched a broad ecosystem with nine initial PCB manufacturing partners to enable customers to easily get the partners’ technology files they need to ensure PCB design manufacturability early in the design process. The goal is to reduce rework, shorten design cycles and accelerate new product introduction.

According to Cadence, design engineer customers have received savings from half to two-thirds fewer technical queries (TQs) from manufacturers when they’ve used the Cadence DesignTrue DFM technology due to using tailor-made spacing, annular ring, copper features and mask rules to assure they are designing the board correctly the first time.

Cadence DesignTrue DFM functionality flags manufacturing rule violations in real time during the PCB layout process with both the Allegro and OrCAD design tools. In contrast, other PCB design tools demand designers wait until the design is complete to do DFM signoff on manufacturing outputs, which often requires significant rework and schedule delays, says Cadence. Nine PCB manufacturers have already become Cadence DesignTrue partners, allowing them to distribute their manufacturing rules to Cadence customers. These include Bay Area Circuits, CircuitHub, Mass Design, Multek, OSH Park, Rocket EMS, Sierra Circuits, Tempo Automation and Würth Elektronik.

Customers can view participating manufacturers and request DesignTrue DFM technology files directly, eliminating the lengthy and error-prone manual entry of hundreds of rules. DFM rules are checked in real time as part of the PCB layout process, reducing the amount of DFM errors found in the manufacturing output. These checks prevent crucial manufacturing errors and limit iterations required to fix such errors.

3D, Multi-Board and More

For its part, Altium typically announces a new version of its Altium Design PCB software once a year. In December, the launch of Altium Designer version 19 introduced a number of new features aimed at enabling a convenient and connected design including multi-board capability, 3D modelling, enhanced HDI, routing automation and more (Figure 3).

Figure 3
Altium Designer version 19 introduces several new features including multi-board capability, 3D modelling, enhanced HDI, routing automation and more.

The version features an advanced Layer Stack Manager. It lets users easily define stackups and exploit comprehensive editing type functionality from the convenience of their layer stack management tool. Routing improvements in version 19 enable designers to complete and perfect routing in a fraction of the time with new capabilities in ActiveRoute like the Move Component feature, Glossing Pushed Routes and Follow Mode.

A new Properties panel in Altium Designer lets designers edit their Thermal Relief settings for one or multiple vias in a single edit action. And support is provided to allow designers to expertly model microvias and HDI stackups on their boards to accommodate high input/output densities of advanced component packages.

Also provided in Altium Designer 19 is a refined documentation process that lets users utilize new, realistic board region views and create highly customizable fabrication and assembly drawings in Draftsman. A real-time BOM (bill of materials) management capability enables you to generate and build comprehensive BOM reports quickly and accurately with access to the latest supplier information and parts availability in ActiveBOM. And new parts search and components panels provide immediate access to component libraries and parts availability from major providers, with the ability to place components directly from the panel.

The new release improves multi-board modeling and collaboration. It simplifies object mating with a single-point selection for each object with MCAD-like editing functionality, powered by a new 3D engine. Version 19 also lets users actualize layer-less design concepts with the ability to print electronic circuits directly onto a substrate that becomes a part of the product.

Front-Loading Design Intent

In the 2018 release of Zuken’s system-level PCB design environment, CR-8000 features were added to support the unique requirements of high-density, high-speed, multi-board designs. With support for system-level engineering and 2D/3D multi-board implementation capabilities, the CR-8000 family of applications spans the complete PCB engineering lifecycle: from system level planning through implementation and design for manufacturability. The CR-8000 environment also includes 3D IC packaging and chip/package/board co-design.

Among the enhancements to the latest version of CR-8000 is the front-loading of design intent (Figure 4). This means enabling efficient front-loading of design constraints and specifications to the design creation process, coupled with sophisticated placement and routing capabilities for physical layout. This increases efficiency and ensures quality through streamlined collaboration across the PCB design chain.

Figure 4
In CR-8000 2018, a front-loading capability enables improved layout control by enabling hardware engineers to assign and edit topology templates and clearance classes to selected signals.

Front-loading of design intent from Design Gateway to Design Force has been achieved by adding an enhanced, unified constraint browser for both applications. This enables hardware engineers to assign topology templates, modify differential signals and assign clearance classes to individual signals. Using a rule stack editor during the circuit design phase, hardware engineers can now load design rules that include differential pair routing and routing width stacks directly from the design rule library into their schematic. Here, they can modify and assign selected rules for improved cross talk and differential pair control. Finally, an enhanced component browser enables component variants to be managed in the schematic, and assigned in a user-friendly table.

In Zuken’s CR-8000 2018, manual routing is supported by a new auto complete and route function that layout designers can use to complete manually routed traces in an automated way. Designers also have the option to look for paths on different layers while automatically inserting vias.

A new bus routing function allows layout designers to sketch paths for multiple nets to be routed over dense areas. An added benefit is the routing of individual signals to the correct signal length as per the hardware engineer’s front-loaded constraints, to meet timing skew and budgets. If modifications to fully placed and routed boards are required, an automatic re-route function allows connected component pins to remain connected with a simple reroute operation during the move process. In all operations, clearance and signal length specifications are automatically controlled and adjusted by powerful algorithms.

Design for Manufacturing

To address manufacturing requirements for high-speed design, CR-8000 2018 enables the automatic stitching of vias in poured conductive areas to be specified in comprehensive detail—for example inside area online, perimeter outline or both inside and perimeter. DFM has been enhanced to include checks for non-conductor items, such as silkscreen and assembly drawing placed reference designators. A design rule check makes sure component reference designators are listed in the same order as the parts for visual inspection accuracy.

Because many product engineers do not work with EDA tools, intelligent PDF documentation is required, especially in 3D. Design Force now supports creation of PRC files commonly used for 3D printing. The PRC files can be opened in PDF authoring applications such as Adobe Acrobat, where they are realized as a 3D PDF file complete with 3D models and bookmarks to browse the design.

There’s no doubt that PCB design tools have advanced way beyond the days when placement and routing were the only duties on their plates. As PCB designs—and the ICs populating them—grow ever more complex, PCB design tool vendors must race to keep up with advanced integrated tool solutions.


Altium |
Bay Area Circuits |
Cadence Design Systems |
Mentor, a Siemens Company |
Zuken |

This article appeared in the June 347 issue of Circuit Cellar

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Infineon, Xilinx and Xylon Team Up for Safety-Critical MCU Effort

Infineon Technologies has announced an effort with Xilinx and Xylon to produce a new Xylon IP core called logiHSSL. It enables high-speed communication between Infineon’s AURIX TC2xx and TC3xx microcontrollers and Xilinx’ SoC, MPSoC and FPGA devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%. The HSSL is an Infineon native interface, low-cost in regards to pin-count because it requires only five pins-–-two LVDS with two pins each and one CLK pin. So far, the HSSL interface is used to exchange data between AURIX devices and customer ASICs for performance or functional extension.

Now, the new IP core will allow system developers to combine safety and security provided by AURIX with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL.

To support development activities the partners are offering a starter kit. It includes a Xilinx evaluation kit, an Infineon AURIX evaluation board and a Xylon FMC board. Kit deliverables include the reference design with the test software application, Xylon’s logicBRICKS evaluation licenses, documentation and technical support.

The new IP core and the development kit will be available this month (March 2019).

Infineon Technologies |
Xilinx |
Xylon |

Non-isolated Up Converters Support High-Performance GPUs

Vicor has announced a 12 V to 48 V non-isolated up converter to support 48 V high-performance GPUs in data centers that are still relying on legacy 12 V power distribution. The 2317 NBM converts 12 V to 48 V with over 98% peak efficiency, 750 W continuous and 1 kW peak power in a 23 mm x 17 mm x 7.4mm surface-mount SM-ChiP package. The NBM (NBM2317S14B5415T00) provides a complete solution with no external input filter or bulk capacitors required. By switching at 2 MHz with ZVS and ZCS, the NBM provides low output impedance and Megahertz-fast transient response to dynamic loads. The NBM incorporates hot-swap and inrush current limiting.

The NBM supports state-of-the-art 48 V input GPUs using Power-on-Package (“PoP”) Modular Current Multipliers (“MCMs”) driven from a 48 V node sourcing a small fraction (1/48th) of the GPU current. Current multiplication overcomes the power delivery boundaries imposed by traditional 12 V systems standing in the way of higher bandwidth and connectivity.

The Vicor Power-on-Package modules build upon Factorized Power Architecture (FPA) systems deployed in high-performance computers and large-scale data centers. FPA provides efficient power distribution and direct conversion from 48 V to 1 V for GPUs, CPUs and ASICs demanding up to 1,000 A. By deploying current multiplication in close proximity to high-current Artificial Intelligence (AI) processors, PoP MCMs enable higher performance and system efficiency.

Vicor |


30 A Encapsulated Digital Power Modules

Renesas Electronics has announced two new fully encapsulated digital DC/DC PMBus power modules that board high power density and efficiency. The dual ISL8274M operates from a 5 V or 12 V power rail, provides two 30 A outputs and up to 95.5% peak efficiency in a compact 18 mm x 23 mm2 footprint. The new ZL9024M operates from a 3.3V rail and outputs 33 A of power in a 17 mm x19 mm2 footprint. They deliver point-of-load (POL) conversions for advanced FPGAs, DSPs, ASICs and memory used in servers, telecom, datacom, optical networking and storage equipment. Both devices are easy-to-use, PMBus-configurable power supplies that include a controller, MOSFETs, inductor and passives encapsulated inside a module that increases available board space and reduces bill of materials (BOM).

The ISL8274M and ZL9024M digital power modules leverage Renesas’ patented ChargeMode control architecture, which provides the highest efficiencies with better than 90% on most conversions. The power modules also provide a single clock cycle fast transient response to output current load steps common in FPGAs and DSPs that process power bursts. Their compensation-free design keeps the modules stable regardless of output capacitor changes due to temperature, variation or aging. Eliminating the need for an external discrete compensation network also saves board space and additional BOM cost. The ISL8274M supports input voltages from 4.5 V to 1 4V, while the ZL9024M accepts input voltages from 2.75 V to 4 V. Both modules offer adjustable output voltages as low as 0.6 V.

The encapsulated modules use Renesas’ proprietary High Density Array (HDA) package, which offers unmatched electrical and thermal performance through a single-layer conductive substrate that reduces lead inductance and dissipates heat primarily through the system board. The HDA’s copper lead-frame structure allows the modules to operate at full load over a wide temperature range with no airflow or heatsinks. The ISL8274M and ZL9024M also provide several protection features that ensure safe operations under abnormal operating conditions, further enhancing their robustness and reliability.

Key Features of the ISL8274M Digital Power Module include:

  • 30 A dual digital switch mode power supply with input voltage range from 4.5 V to 14 V and programmable Vout from 0.6 V to 5 V
  • PMBus-enabled solution for full system configuration, telemetry and monitoring of all conversions and operating parameters
  • Programmable Vout, soft-start, soft-stop, sequencing, margining and under-voltage, over-voltage, under-current, over-current, under temperature and over-temperature
  • Monitors Vin, Vout, Iout, temperature, duty cycle, switching frequency, and faults
  • Power good indicator, and ±1.2% Vout accuracy over line, load, and temperature
  • Pin-strap mode using external resistors for standard settings
  • Internal nonvolatile memory saves module configuration parameters and fault logging

Key Features of the ZL9024M Digital Power Module include:

  • 33 A digital switch mode power supply with input voltage range from 2.75 V to 4 V and programmable Vout from 0.6 V to 1.5 V
  • PMBus-enabled solution for full system configuration, telemetry and monitoring of all conversions and operating parameters
  • Programmable Vout, soft-start, soft-stop, sequencing, margining and under-voltage, over-voltage, under-current, over-current, under temperature and over-temperature
  • Monitors Vin, Vout, Iout, temperature, duty cycle, switching frequency and faults
  • Power good indicator, and ±1.2% Vout accuracy over line, load, and temperature
  • Pin-strap mode using external resistors for standard settings
  • Internal nonvolatile memory saves module configuration parameters and fault logging


The ISL8274M is available now in a thermally enhanced 18 mm x 23 mm x 7.5 mm HDA package, and is priced at $39 (1,000). An ISL8274MEVAL1Z evaluation board is available for $150.

The ZL9024M is available now in a thermally enhanced 17 mm x 19 mm x 3.5 mm HDA package, and is priced at $29 (1,000s). The ZL9024MEVAL1Z evaluation board is available for $95.

Renesas Electronics |

Quad Channel DPWM Step-Down Controller

Exar Corp. has introduced the XR77128, a universal PMIC that drives up to four independently controlled external DrMOS power stages at currents greater than 40 A for the latest 64-bit ARM processors, FPGAs, DSPs and ASICs. DrMOS technology is quickly growing in popularity in telecom and networking applications. These same applications find value in Exar’s Programmable Power technology which allows low component count, rapid development, easy system integration, dynamic control and telemetry. Depending on output current requirements, each output can be independently configured to directly drive external MOSFETs or DrMOS power stages.EX045_XR77128

The XR77128 is quickly configured to power nearly any FPGA, SoC, or DSP system through the use of Exar’s design tool, PowerArchitect, and programmed through an I²C-based SMBus compliant serial interface. It can also monitor and dynamically control and configure the power system through the same I²C interface. Five configurable GPIOs allow for fast system integration for fault reporting and status or for sequencing control.  A new Arduino-based development platform allows software engineers to begin code development for telemetry and dynamic control long before their hardware is available.

The XR77128 is available in a RoHS-compliant, green/halogen free space-saving 7 mm × 7 mm TQFN. It costs $7.75 in 1000-piece quantities.

Source: Exar Corp.

Configurable Regulator

LinearThe LTM4644 quad output step-down µModule (micromodule) regulator is configurable as a single (16-A), dual (12-A, 4-A, or 8-A, 8-A), triple (8-A, 4-A, 4-A), or quad (4-A each) output regulator. This flexibility enables system designers to rely on one simple and compact µModule regulator for the various voltage and load current requirements of FPGAs, ASICs, and microprocessors as well as other board circuitry. The LTM4644 is ideal for communications, data storage, industrial, transportation, and medical system applications.

The LTM4644 regulator includes DC/DC controllers, power switches, inductors and compensation components. Only eight external ceramic capacitors (1206 or smaller case sizes) and four feedback resistors (0603 case size) are required to regulate four independently adjustable outputs from 0.6 to 5.5 V. Separate input pins enable the four channels to be powered from a common supply rail or different rails from 4 to 14 V.

At an ambient temperature of 55°C, the LTM4644 delivers up to 13 A at 1.5 V from a 12-V input or up to 14 A with 200-LFM airflow. The four channels operate at 90° out-of-phase to minimize input ripple whether at the 1-MHz default switching frequency or synchronized to an external clock between 700 kHz and 1.3 MHz. With the addition of an external bias supply above 4 V, the LTM4644 can regulate from an input supply voltage as low as 2.375 V. The regulator also includes output overvoltage and overcurrent fault protection.

The LTM4644 costs $22.85 each in 1,000-unit quantities.

Linear Technology Corp.