3D Tool Strengthens Marriage of PCB Design with Mechanical Design

Cadence Design Systems has announced its Cadence Sigrity 2018 release, which includes new 3D capabilities that enable PCB design teams to accelerate design cycles while optimizing cost and performance. According to the company, a 3D design and 3D analysis environment integrating Sigrity tools with Cadence Allegro technology provides a more efficient and less error-prone solution than current alternatives using third-party modeling tools, saving days of design cycle time and reducing risk.

In addition, a new 3D Workbench methodology bridges the gap between the mechanical and electrical domains, allowing product development teams to analyze signals that cross multiple boards quickly and accurately.

Since many high-speed signals cross PCB boundaries, effective signal integrity analysis must encompass the signal source and destination die, as well as the intervening interconnect and return path including connectors, cables, sockets and other mechanical structures.

Traditional analysis techniques utilize a separate model for each piece of interconnect and cascade these models together in a circuit simulation tool, which can be an error-prone process due to the 3D nature of the transition from the PCB to the connector. In addition, since the 3D transition can make or break signal integrity, at very high speeds designers also want to optimize the transition from the connector to the PCB or the socket to the PCB.

According to the company, the Sigrity 2018 release enables designers to take a holistic view of their system, extending design and analysis beyond the package and board to also include connectors and cables. An integrated 3D design and 3D analysis environment lets PCB design teams optimize the high-speed interconnect of PCBs and IC packages in the Sigrity tool and automatically implement the optimized PCB and IC package interconnect in Allegro PCB, Allegro Package Designer or Allegro SiP Layout without the need to redraw.
Until now, this has been an error-prone, manual effort requiring careful validation. By automating this process, the Sigrity 2018 release reduces risk, saves designers hours of re-drawing and re-editing and can save days of design cycle time by eliminating editing errors not found until the prototype reaches the lab. This reduces prototype iterations and potentially saves hundreds of thousands of dollars by avoiding re-spins and schedule delays.

A new 3D Workbench utility available with the Sigrity 2018 release bridges the mechanical components and the electronic design of PCB and IC packages, allowing connectors, cables, sockets and the PCB breakout to be modeled as one with no double counting of any of the routing on the board. Interconnect models are divided at a point where the signals are more 2D in nature and predictable. By allowing 3D extraction to be performed only when needed and fast, accurate 2D hybrid-solver extraction to be performed on the remaining structures before all the interconnect models are stitched back together, full end-to-end channel analysis can be performed efficiently and accurately of signals crossing multiple boards.

In addition, the Sigrity 2018 release offers Rigid-Flex support for field solvers such as the Sigrity PowerSI technology, enabling robust analysis of high-speed signals that pass from rigid PCB materials to flexible materials. Design teams developing Rigid-Flex designs can now use the same techniques previously used only on rigid PCB designs, creating continuity in analysis practices while PCB manufacturing and material processes continue to evolve.

Cadence | www.cadence.com

MCU Enables 3D Graphics in Car Displays

Cypress Semiconductor has announced a new series in its Traveo automotive microcontroller family with more memory to support a hybrid instrument cluster with 3D graphics and up to 6 traditional gauges, as well as a head-up display. The highly integrated, single-chip devices in the S6J32xEK series include an advanced 3D and 2.5D graphics engine and provide scalability with Cypress’ low-pin-count HyperBus memory interface. The series continues Cypress’ expansion of its broad automotive portfolio with differentiated system performance via its MCUs, wireless radios, capacitive-touch solutions, memories and Power Management ICs (PMICs).
Cypress Traveo Automotive MCUs 2017

The Traveo S6J32xEK series integrates up to 4MB of high-density embedded flash, 512 KB RAM and 2 MB of Video RAM, an ARM Cortex-R5 core at 240 MHz performance, a Low-Voltage Differential Signaling (LVDS) video output, a Low-Voltage Transistor-Transistor Logic (LVTTL) video output and a 6x stepper motor control. This combination enables the devices to serve as single-chip solutions to drive two displays. The devices have up to two 12-pin HyperBus memory interfaces that dramatically improve read and write performance of graphical data and other data or code.

A single HyperBus interface can be used to connect to two memories for Firmware Over-The-Air (FOTA) updates, which enable end-users to get software fixes and new features and applications for their vehicles on-the-go. The devices support all in-vehicle networking standards required for instrument clusters, including Controller Area Network-Flexible Data (CAN-FD) and Ethernet AVB. Additionally, the series provides robust security with integrated enhanced secure hardware extension (eSHE) support.

The Traveo S6J32xEK series include 50 channels of 12-bit Analog to Digital Converters (ADC), 12 channels of multi-function serial interfaces and I2S interfaces with an audio to output the complex, high-quality sounds required in today’s instrument clusters. The devices’ support for Ethernet AVB delivers increased bandwidth in multimedia applications and reduced programming time. The S6J32xEK series offers functional safety features to support Automotive Safety Integrity Level (ASIL) B, and the devices feature a wide ambient temperature range of -40˚C to +105˚C. The Traveo family is backed by a comprehensive tools and software ecosystem that simplifies system integration, including AUTOSAR MCAL 4.0.3 support.

The Traveo S6J32xEK series is sampling now and will be in production in the first quarter of 2018. The MCUs are available in a 208-pin and 216-pin thermally enhanced quad flat package (TEQFP).

Cypress Semiconductor | www.cypress.com