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FPGA/PC Streaming Made Simple

Written by Enclustra

A Universal Connection Between an FPGA and a PC

Streaming data between a PC and an embedded device—such as a camera or a data acquisition frontend—is one of the most common FPGA applications. Depending on the system requirements, different interfaces like Ethernet, USB or PCI Express can leverage their advantages, be they high bandwidth, low latency or very long cables. Built for exactly for those needs, Enclustra has developed an IP solution with a clean and simple API on the PC side, as well as an AXI4 interface to which you can connect FPGA logic.

In many FPGA-based applications—whether you’re writing configuration data, reading measurements or streaming data—a host needs to access a programmable device (Figure 1). In a typical application, the data preprocessing is done in the FPGA while the data presentation is done on a host PC. Written in a high-level language like C#/.NET or C++, the host application may also configure the FPGA.

FIGURE 1
Many FPGA applications involve communicating with a host PC.

Communication is Everywhere
Three types of communication patterns are very common in FPGA-based applications:

  1. Streaming: Data streaming between the FPGA and the PC, typically used for data preparation (FPGA to PC) or data processing (PC to FPGA)
  2. Memory Mapped Access: Register access on the FPGA by the PC, typically used for writing configuration data or polling status information
  3. Signaling: Event signaling from the FPGA to the PC, typically Interrupts for signaling completion, errors, etc.

A few real-life examples illustrate the use of one or several of the above explained communication patterns in an application.

Smart High-Speed Camera
With their high data rates, massive parallelism and flexible interfaces, FPGAs are the perfect technology for all kinds of vision applications—like a smart camera with edge detection, for example. Enclustra was tasked to develop a solution to detect the position of a projected laser line. The solution needed to measure a profile with extreme precision while at very high refresh rates (Figure 2). The high picture resolution and frame rates required the images to be preprocessed in the FPGA. For controlling and surveying the measurement process, the preprocessed images are streamed to a remotely installed PC via Gigabit Ethernet. Besides the image, the results of the edge detection are also transferred to the PC. The host Software and the GUI are programmed in C#.

FIGURE 2
Vision application streaming the (preprocessed) images to the host PC

Monitoring and Configuration of Drive Controller
Conventional motion applications use a Digital Signal Processor (DSP) for the control loops. If very high control loop rates or a lot of motor axes are needed, DSPs are pushing against their limits. Also, very high PWM frequencies can be challenging to achieve. But those situations are exactly where FPGAs excel. The Universal Drive Controller IP Core from Enclustra, for example, supports up to 8 drives per controller at up to 200kHz control rate—even in a small and low cost FPGA (Figure 3). And the PWM frequency is only limited by the maximum toggle rate of the output pins.

Meanwhile, tasks such as the configuration of the motion vectors and the status monitoring are most conveniently done with a PC—whether an embedded or industrial PC. Because the FPGA is taking care of all the real-time critical tasks, there is no need to use a real time operating system and the user application can be written in a high-level language like C++, C# or C.

The configuration and monitoring of the drive controller are realized with simple, memory mapped read and write accesses. At the same time, the drive controller can send alarms or events to the user application—for example if a motor is drawing too much current or overheating.

FIGURE 3.
By processing the real-time tasks for the motion control in an FPGA,
a standard PC without real-time OS can be used.

The FPGA is the Accelerator
For most applications, standard processors provide more than enough computing power. Nevertheless, there are still many applications where an external accelerator is needed. The most common of these is the GPU, using it to handle all the graphics calculation and processing. For more specific applications, an FPGA may be the more optimal solution, like for the encryption and decryption of network traffic in real time (Figure 4). The PC is sending the data stream to the FPGA, that is integrated on a PCIe card. The FPGA encrypts and transfers the processed data into the main memory of the PC trough DMA. This reduces both the latency and the processor load to a minimum. Here again, the configuration of the FPGA is done with memory-mapped read and write accesses from the host PC.

Thanks to system-on-chips (SoCs) that integrate an FPGA with Arm CPUs—like the Xilinx Zynq UltraScale+ MPSoC or the Intel Arria 10 families—such a system now can be implemented even in a single chip.

FIGURE 4.
Here, the PC is sending the data stream to the FPGA that is integrated on a PCIe card. The FPGA encrypts and transfers the processed data into the main memory of the PC trough DMA. This reduces both the latency and the processor load to a minimum.

Communication Solution Bucket List
The examples above have shown that a communication solution between an FPGA and PC must fulfil many requirements:

Data Streams:

  • Support frame as well as byte streams
  • Append metadata to a data stream (e.g. timestamps)

Memory Mapped Access:

  • Support read, write as well as read-modify-write accesses
  • Allow a single access but also bursts

Signaling:

  • Support interrupts
  • React to edge and level changes of signals
  • Handle interrupts with different priorities

It would also be convenient if different interfaces could be supported, like PCIe, USB and Ethernet. This also leads to the requirement for the same API and interface logic inside the FPGA, no matter which interface, communication type, operating system or FPGA are used.

Often, different parts of an application need to communicate with the FPGA at the same time, so multiple connecting channels need to share one physical link. An example is 3 data stream channels, 2 Memory Mapped channels and 2 Signaling channels “talking” at the same time with the FPGA over the same USB 3.0 link. A sophisticated flow control mechanism is needed to keep the bandwidth high, and the latency and CPU load low at the same time. And also, blocking and nonblocking transfers need to be handled by the flow control.

In the case of a non-fatal error, there should be a recovery strategy and, if a fatal error occurs, it has to be decided how to return the system to a safe state. An example is deciding when and how fast rotating motors should be stopped.

Communication, Made Simple
Aside from all the above-mentioned requirements there are several more challenges. Our purpose was examining the communication with an FPGA. Beyond that, the actual application still has to be developed. In other words, communication with the FPGA is often only a means to an end.

FIGURE 5
The FPGA Manager IP solution is a simple-to-use drop-in solution for all PC to FPGA communication.

Enclustra was confronted with exactly these same challenges when its FPGA experts were implementing different customer projects. That’s why the Switzerland-based Enclustra FPGA experts decided to develop the FPGA Manager IP Solution—to cover exactly all those requirements (Figure 5). The FPGA Manager IP Solution enables simple and efficient data transfer between a host PC and an FPGA via USB 3.0, Gigabit Ethernet or PCI Express.

The solution includes a host software library (DLL) and an IP core for the FPGA. The user application communicates with the FPGA via a simple API with read/write commands that hide the complexity of the underlying protocol. Streaming and memory-mapped accesses are supported, as well as signaling. It runs on Windows and Linux and supports various high-level languages (C # /. NET, C / C ++, Matlab) as well as different processor architectures (x86, Arm).

A unified software API and firmware interface for all different links, operating systems, high level languages and FPGAs minimizes the effort required for integration or porting a system to a new platform. Regardless of the protocol used—be it PCI Express, USB or Ethernet—the API in the user application on the host PC as well as the interface between the IP core and the user logic in the FPGA stay the same. In other words, the protocol can be swapped without modifying the software or user logic.

Enclustra uses its own FPGA Manager IP Solution regularly for customer projects, but is also offering it as a standalone IP Solution—whether used together with an Enclustra FPGA or SoC Module or a customer-specific solution. That’s what we call streaming, made simple.

Enclustra is an innovative and successful Swiss FPGA design company. With the FPGA Design Center, Enclustra provides services covering the whole range of FPGA-based system development: From high-speed hardware or HDL firmware through to embedded software, from specification and implementation all the way to prototype and series production.

In the FPGA Solution Center, Enclustra develops and markets highly-integrated FPGA modules and FPGA-optimized IP cores.

By specializing in forward-looking FPGA technology, and with broad application knowledge, Enclustra can offer ideal solutions at minimal expense in many areas. More information can be found at: www.enclustra.com

Enclustra GmbH – Everything FPGA.
Räffelstrasse 28, 8045 Zürich
Switzerland
Tel. 043 343 39 43, Fax 043 343 39 44
[email protected], www.enclustra.com


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