# PWM DAC Ripple Reduction

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A common way of producing an analogue control signal from a microcontroller is to use a PWM output and an RC filter. This can be much cheaper than an external DAC for non-critical applications. Figure 1 shows how this works. The time constant of the R1C1 low-pass filter is set to be much longer than the PWM period to produce a DC voltage that is the average of the input voltage and proportional to the PWM duty cycle. There will of course be some amount of undesirable PWM-frequency ripple on the output. To reduce this ripple, we need a increase the filter time constant.

The downside of having a long time constant is the slow response of the output voltage to changes in the PWM duty cycle. Stephen Woodward published a really neat technique to address this trade off in an article published in EDN in 2017. Equation 1 below describes the worst-case (50% duty cycle) peak to peak ripple.

Where TPWM is the PWM period and VS is the full-scale voltage. The ripple will be small if the RC time constant is much greater than the PWM period. Woodward shows that the time to for the output voltage to settle to a level equal to the ripple voltage for a given change in duty cycle is:

If we take the case where we want an 8-bit resolution DAC, and we assume the peak-to-peak ripple should be limited to one LSB (i.e., Vripple = VS / 256), Equation 1 tells us that we will need an RC time constantequal to64 TPWM. The settling time (from Equation 2) will be 355×TPWM. This is a long time! For a 10 kHz PWM carrier we will have a settling time of 35ms. If we wanted 10-bit resolution, the settling time would be even worse at 177ms.

Woodward’s solution is shown in Figure 2. Here an inverted version of the PWM signal is injected into the output voltage to cancel the ripple. If we set R2 = R1 and C2 = C1, the new equations for ripple and settling time will be:

Using the 8-bit example above, the required RC time constant reduces from 64 TPWM to just 4 TPWM and the settling time reduces from 355 TPWM to 44 TPWM (or 4.4ms at 10kHz). This is an eightfold improvement! In the 10-bit case, the settling time reduces to 11ms from 177ms for the original circuit.

Is this too good to be true? Maybe this level of ripple reduction is sensitive to component matching? Analysis by Horowitz and Hill shows that it is sufficient to use 1% tolerance resistors and 10% tolerance capacitors to achieve these results. The benefit in terms of ripple reduction is well worth the few cents in extra components. Many microcontrollers offer PWM generators with complimentary outputs so it may not even be necessary to use and external inverter to get the benefits of this simple yet elegant circuit.

References

“Cancel PWM DAC Ripple with Analog Subtraction – EDN.” Accessed July 6, 2022. https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction/.

Horowitz, Paul, Winfield Hill, and Paul Horowitz. The Art of Electronics: The X-Chapters. Cambridge ; New York, NY: Cambridge University Press, 2020.

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