Quick Bits Resources

MIPI Display Serial Interface

Written by Andrew Levido
(CLICK TO ENLAGE)
FIGURE 1. The MIPI Alliance has defined a plethora of interfaces for use in mobile devices. This article focuses on the Display Serial Interface (DSI) shown in the upper left corner.

The MIPI Alliance is a consortium of mobile device manufacturers and electronics components vendors that was established in 2003 to specify a common set of interfaces for various sub-systems within smartphones and similar multimedia devices. They have published a range of standards covering interfaces to audio, camera, display, touchscreen and other devices as shown in their infographic (Figure 1).

One of these, the Display Serial Interface, or DSI, standard is starting to appear on readily available microcontrollers (MCUs) and displays. I have recently embarked on my first project that uses this interface, so it’s worth sharing some of what I have learned in the process.

The DSI is a high-speed serial interface between a host processor and a display module. It is designed for low pin count, high bandwidth and low EMI. We will focus on the basic features of the DSI physical layer, called the D-PHY and touch briefly on the next layer up, the Display Command Set or DCS. Figure 2 shows two ways DSI can be used. It can operate in video mode where RGB pixel data and horizontal and vertical sync signals provided by the display controller are encoded into the serial stream by the DSI Host and decoded by the Device to drive the display glass. Alternatively, if the display controller and graphics RAM are integrated into the display, DSI can operate in command mode where data being written by the MCU into the RAM is encoded on the interface. In either mode commands from the DCS can be transmitted to configure the display.

(CLICK TO ENLARGE)
FIGURE 2. The DSI interface can operate in two modes – video mode in which the pixel data and synchronization signals are streamed to the display in real-time, and command mode in which pixel data is written to the graphics RAM integrated with the display controller in the display module.

The physical layer consists of one double data rate high-speed clock lane and one or more data lanes. Each lane operates as a high-speed, low-swing differential pair in high-speed (HS) mode, capable of transferring data at up to 1Gbps. This is High Speed, or HS mode. In this mode the voltage swing is around 200 mV peak to peak and data can only be transferred from the host to the device. Data lane zero however, is also capable of low-speed bidirectional signalling in single ended mode across each line of the pair. This is known as Low Power, or LP mode. Here the voltage swing is higher, typically 1.2V and the data rate is typically around 10Mbps to 20Mbps.

The two data lane zero line, D0P and D0N, can take one of four states, LP-00, LP-01, LP-10 and LP-11. Certain sequences of these states are used to switch between three possible modes – control mode, high-speed transmission, and escape mode. Control mode is the idle state from which the other states begin and end. On power-up the DSI is in control mode and the LP-11 idle state.

(CLICK TO ENLARGE)
FIGURE 3. Data Lane 0 is capable of supporting both high speed differential signals at up to 1Gbps and low power bidirectional single-ended signaling. LP signaling uses 1.2V logic levels while the HS signaling is typically a 200mV swing around a 200mV common mode level.

Figure 3 shows how a transition from LP to HS signaling and back occurs. The sequence LP-11, LP-01, LP-00 initiates the transition. The host switches on its HS drivers and outputs a synchronization sequence followed by the data. We’ll look at the data format later. To conclude the transmission and return to the control state, the host outputs a trailing sequence of ones or zeroes then returns the two data lines to the LP-11 state. In HS mode the data is split across the data lanes, if there are more than one. For example, with two data lanes even bytes will be transmitted on lane 0 and odd bytes on lane 1 at the same time, doubling the throughput.

— ADVERTISMENT—

Advertise Here

Escape mode is used to enter low-power data transmission mode, enter an ultra-low-power sleep mode or indicate certain trigger conditions. Figure 4 shows an example of entering low power data transmission mode. The escape mode is entered via the sequence LP-11, LP-10, LP-00, LP-01, LP-00, and exited via the sequence LP-01, LP-11. In escape mode data is transmitted using “one-hot coding” where a one bit is indicated by an LP-01, LP-00 sequence and a zero bit is indicated by the sequence LP-10, LP-00. This coding allows the device to recover the LP signalling clock by exclusive-OR-ing the two signals.

(CLICK TO ENLARGE)
FIGURE 4. Commands can be sent over Data Lane 0 using LP data transmission by first sending an escape sequence and then a Low Power Transmission Entry Command. Data is then sent in long or short packets as described in the text. Such communication is usually used to initialize the display at power up.

After sending the escape sequence the Host sends an 8-bit entry command. This will be 11100001 in the case of low-power data transmissions. Other entry commands are available for other escape actions not discussed here.

(CLICK TO ENLARGE)
FIGURE 5. Data is sent in the form of short fixed-length packets or long variable-length packets in both HS and LP modes. Data is sent LSB first. The Data ID byte indicates the type of packet and the format of the data it contains.

Data transmissions, whether transmitted in HS or LP mode use the same packet format and are sent LSB first. Data can be sent in short 32-bit packets or long variable length packets as shown in Figure 5. Each packet begins with a Data ID byte which indicates the type of packet and contents. Table 1 below lists the possible Data ID values and the type of packet they represent. Not all devices will respond to all Data ID values. Packets are ignored by devices that do not support any particular ID.

Data type Description Packet DSI mode
0x01 Sync event, V sync start Short Video
0x11 Sync event, V sync end Short Video
0x21 Sync event, H sync start Short Video
0x31 Sync event, H sync end Short Video
0x08 End of Transmission Packet Short Video
0x02 Color Mode OFF Short Video
0x12 Color Mode On Short Video
0x22 Shut down peripheral command Short Video
0x32 Turn ON peripheral Short Video
0x03 Generic short write 0 parameters Short Command
0x13 Generic short write 1 parameters Short Command
0x23 Generic short write 2 parameters Short Command
0x04 Generic short read 0 parameters Short Command
0x14 Generic short read 1 parameters Short Command
0x24 Generic short read 2 parameters Short Command
0x05 DCS short write 0 parameters Short Command
0x15 DCS short write 1 parameters Short Command
0x06 DCS short read 0 parameters Short Command
0x37 Set maximum return packet size Short Command
0x09 Null packet, no data Long Video
0x19 Blanking packet, no data Long Video
0x29 Generic long write Long Command
0x39 DCS long write Long Command
0x0C Loosely packed pixel stream 20-bit YCbCr Long Video
0x1C Packed pixel stream 24-bit YCbCr Long Video
0x2C Packed pixel stream 16-bit YCbCr Long Video
0x0D Packed pixel stream 30-bit RGB Long Video
0x1D Packed pixel stream 36-bit RGB Long Video
0x3D Packed pixel stream 12-bit YCbCr Long Video
0x0E Packed pixel stream 16-bit RGB Long Video
0x1E Packed pixel stream 18-bit RGB Long Video
0x2E Loosely packed pixel stream 18-bit RGB Long Video
0x3E Packed pixel stream 24-bit RGB Long Video
TABLE 1. Possible Data ID values and the type of packet they represent

Short packets consist of 4 bytes—a data ID byte, two data bytes and a checksum byte. Short packets are typically be used for commands that have zero or one parameter and video sync events. Long packets have a 4-byte header consisting of the Data ID, 16-bit packet length and checksum. This is followed by the data stream. Long packets are used for commands that have more than one parameter and for the pixel stream.

There is a lot more to the MIPI DSI interface that we don’t have space for here. This overview has hopefully given you a flavour for this interesting interface. It is a lot more complex than the classic parallel RGB plus clock and sync signals, but it requires a lot fewer pins and is capable of much higher bandwidth and therefore driving larger, high resolution displays.

References

MIPI. “MIPI Display Serial Interface (MIPI DSI),” December 9, 2016. https://www.mipi.org/specifications/dsi.

STM Microelectronics. “AN4860. Application note. DSI Host on STM32F469/479, STM32F7x8/x9 and STM32L4R9/S9 MCUs” February 10, 2017. https://www.st.com/resource/en/application_note/dm00287601-dsi-host-on-stm32f469-479-stm32f7x8-x9-and-stm32l4r9-s9-mcus-stmicroelectronics.pdf

Keep up-to-date with our FREE Weekly Newsletter!

Don't miss out on upcoming issues of Circuit Cellar.

— ADVERTISMENT—

Advertise Here


Note: We’ve made the May 2020 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

Would you like to write for Circuit Cellar? We are always accepting articles/posts from the technical community. Get in touch with us and let's discuss your ideas.

Sponsor this Article
+ posts

Andrew Levido (andrew.levido@gmail.com) earned a bachelor’s degree in Electrical Engineering in Sydney, Australia, in 1986. He worked for several years in R&D for power electronics and telecommunication companies before moving into management roles. Andrew has maintained a hands-on interest in electronics, particularly embedded systems, power electronics, and control theory in his free time. Over the years he has written a number of articles for various electronics publications and occasionally provides consulting services as time allows.

Supporting Companies

Upcoming Events


Copyright © KCK Media Corp.
All Rights Reserved

Copyright © 2022 KCK Media Corp.

MIPI Display Serial Interface

by Andrew Levido time to read: 6 min