Most of the time when we are designing with digital logic, we consider logic states (zero or one, true or false), rather than the precise voltage levels in the circuit. This abstraction is extremely useful as it allows us to build circuits with very complex behaviors with relative ease. Nevertheless, as electronics designers we do need to be concerned about the underlying details, since the validity of the abstraction depends on it.
When we connect two digital signals, we need to be sure that the level of a logic high or low is unambiguously understood, even in an imperfect environment where there may be electrical noise, power supply ripple or the like. This is more or less taken care of for us in the case of signals between devices of the same logic family, but as soon as we need to connect a variety of logic devices or contend with multiple voltage levels, we really need to pay attention to logic voltage levels. We often hear the term “TTL level” in this context, so let’s start there.
Figure 1 shows the logic level characteristics for old-school bipolar Schottky TTL. This is still readily available, despite being released in the mid 1970s. In this case the data is from a TI SN74S00 quad 2-input NAND gate although all other members of the “74S” family should be compatible, even if produced by different manufacturers.
Here is the logic level data extracted from the datasheet for old school bipolar TTL logic.
Below the table is a diagram that shows the same data in graphical form. The output characteristic is shown above the line, and the input thresholds are shown below the line. You can also use this type of diagram to work out whether different logic families or devices will work together.
At the top is the relevant data sheet extract and, below, is a graphical representation of the logic level data. Here the output characteristic is shown above the horizontal line. A logic low output is guaranteed to be below VOL (0.35V), as long as the load remains within specifications (sinking < 8mA in this case). A logic high output is guaranteed to be above VOH (2.7V) if we are sourcing less than 0.4 mA. Note that any output voltage between GND and VOL is a valid logic low and any voltage between VOH and VCC is a valid logic high. Output values between VOL and VOH are invalid.
The input characteristic is shown below the line. In this case any voltage between GND and VIL (0.8V) will be interpreted as a logic low and any voltage between VIH (2.0V) and VCC will be interpreted as a logic high. The logic level detected if the input voltage is between VIL and VIH is undefined. You can see that the valid input ranges are wider than the valid output ranges. This is really important for noise immunity. There should be no possibility that a valid logic level will be misinterpreted, even in the presence of a few hundred millivolts of noise.
You will also note that the logic level characteristic and the output source/sink capability is not symmetrical. This is a result of the architecture of bipolar TTL logic where an output must sink current from an input to drive a logic low. Contemporary CMOS logic families such as 4000B series with high-impedance inputs had symmetric thresholds as shown in Figure 2. The high input impedance means the outputs don’t have to source or sink much current, so the output voltages are much closer to the supply rails. This logic family can operate over a much wider voltage range than TTL, but even with VCC of 5V you can see that the noise immunity is significantly better than for TTL.
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This is the logic level diagram for 4000B-series CMOS when operating at 5V. You can see that the output levels are very close to the supplies and that, unlike TTL logic, the input thresholds are symmetrical. Many modern CMOS 7400-series families have similar symmetrical input thresholds.
This leads us to the most useful application of diagrams such as this. By comparing Figure 1 and Figure 2 you will see that if you were to drive a 4000B series CMOS input from a 74LS TTL output, you could have the situation where a valid TTL VOH of 2.7V does not meet the minimum 3.5V VIH threshold of the CMOS input. This connection may result in unpredictable results and must be avoided.
Of course, you would not use a bipolar TTL family for a new design today. These have long been superseded by CMOS equivalents with much better specifications. Initially CMOS implementations of 74-series logic families were offered two versions, one with symmetrical CMOS-type thresholds and another with TTL-type thresholds for compatibility with legacy TTL circuits. For example, the 74HC/74HCT and 74AHC/74AHCT families. Figure 3 shows their input-output characteristics.
Some CMOS logic families come in two variants – one with CMOS-type thresholds and one with logic levels matching legacy bipolar TTL for compatibility. The TTL compatible version is usually distinguished by the “T” in the family name.
The “T” variants have the asymmetric input thresholds necessary to interface with bipolar TTL outputs. You will note that unlike the previous example, both variants can be used together, although only the “T” variant is compatible with legacy TTL logic levels.
When designing new logic circuits today, I would recommend using one of the newer logic families – and you will absolutely need to do so if using 3.3V or lower supplies. In these cases, you almost certainly do not care about matching ancient bipolar TTL thresholds.
I typically use a logic family such as the 74LVC or 74VCX families. These have a VCC range of 1.2 to 3.6V. The former has 5V tolerant inputs and the latter has 3.6V tolerant inputs which can be handy if level-shifting is required. Figure 4 shows the input-output characteristic for these devices at 3.3V and 1.8V respectively. Of course, these are just two of the plethora of logic families worth considering.
Here are the logic level diagrams for two modern logic families that will work at voltages below 5V. Note that in both cases the inputs are tolerant of input levels above the supply voltage. This is really handy for level-shifting in circuits with multiple supply voltages.
Just keep in mind that high and low logic levels are an abstraction that means different things for different device families. It’s well worth the few minutes it takes to make sure that all your digital devices will play nicely together. I find that drawing a few input-output characteristic diagrams helps in this regard. Only then can you be certain that the abstraction from voltage levels to logic states will be valid.
References
“74VCX00 – Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs,” https://www.onsemi.com/pdf/datasheet/74vcx00-d.pdf
“74LVC00A – Quad 2-input NAND Gate”,
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https://assets.nexperia.com/documents/data-sheet/74LVC00A.pdf
“SN7400, SN74LS00, SN74S00 Quadruple 2-input Positive-NAND Gates” https://www.jaycar.com.au/medias/sys_master/images/images/9683222364190/ZS5000-dataSheetMain.pdf
“Logic Guide” Texas Instruments, 2017 https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf?ts=1660107176031&ref_url=https%253A%252F%252Fwww.google.com%252F
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Andrew Levido (andrew.levido@gmail.com) earned a bachelor’s degree in Electrical Engineering in Sydney, Australia, in 1986. He worked for several years in R&D for power electronics and telecommunication companies before moving into management roles. Andrew has maintained a hands-on interest in electronics, particularly embedded systems, power electronics, and control theory in his free time. Over the years he has written a number of articles for various electronics publications and occasionally provides consulting services as time allows.
