Dual slope analog to digital converters are a type of integrating ADC frequently used in precision multimeters. They have high precision and good stability at relatively low cost. They can also provide very good rejection of power line interference.
To understand the dual slope converter architecture, it is helpful to start with the simpler single slope example as shown in Figure 1. Initially, a logic circuit (shown as a block on the right) holds the analog switch closed so the output of the integrator is zero and the output of the comparator is low. When a start signal is provided, a counter is started, and the analog switch opened. The counter counts pulses from some high-frequency digital clock internal to the digital block.
The single-slope ADC shown here is simple but suffers from a number of drawbacks – not least its dependence on the stability and precision of the capacitor value and clock speed.
The integrator’s output voltage begins to rise linearly until it reaches the same level of the input voltage, at which point the comparator output goes high, halting the counter in the logic circuit and resetting the integrator. The maximum counter value is therefore proportional to the time required for the integrator voltage to ramp up to the Vin. This ramp time (tru) is itself proportional to Vin , the resistor and capacitor values and the reference voltage.
While this circuit is relatively simple, it suffers from a number of drawbacks. Its accuracy is dependent on the value and stability of the capacitor – which is a problem because precision capacitors are rare and expensive. The precision of this circuit is also highly dependent on the comparator, with any offset voltage or offset drift contributing to errors. In addition, any variance in the clock rate will impact the digital reading.
The solution to all of these problems is the dual slope converter shown in Figure 2. This time when the conversion is initiated, the (negative) input voltage is applied to the integrator for a fixed number of clock cycle corresponding to the period (tru). This period starts when the comparator output falls for the reason we will see below. During this phase the integrator voltage to ramp up to some value VC. At the end of the fixed period, the analog switch flips, the counter is restarted, and the reference voltage is applied to the integrator causing the output voltage to ramp down again. When it reaches zero, the comparator output goes high, and the counter is stopped. The counter therefore measures the time taken for the integrator voltage to ramp down to zero (trd).
The dual-slope analog to digital converter shown here overcomes most of the drawbacks of the single-slope architecture. It is largely unaffected by capacitor or clock frequency instability.
Its pretty easy to show that trd is proportional to Vin, Vref , the ratio of the input resistors and the ramp-up time tru. The capacitance neatly cancels out of the equation. This means the dual-slope ADC is not dependant on capacitor tolerance meaning a reasonably-priced component can be used. That said, for best results you should use a quality cap with low dielectric absorption in the integrator. Polypropylene or polystyrene are good choices.
It also easy to see that, unlike the single-slope converter, the dual-slope converter is not dependant on the precision of the clock frequency. Assuming the counters determining tru and measuring trd are clocked by the same clock, any errors in the frequency will be cancelled out.
If, for example the clock was 5% slower than nominal, the tru period would be extended by that amount and the peak integrator voltage would similarly be 5% greater. The time taken to ramp down from this higher voltage would also be 5% longer, resulting in the same count with the lower clock rate or the nominal one. As long as the clock remains stable over the measurement cycle the actual clock frequency is not critical.
Similarly, the dual slope converter is less sensitive to comparator offset and drift since the counting of both ramp-up and ramp-down times are influenced by a comparator output transition.
The dual slope converter can also provide very good rejection of power line interference if the fixed part (the ramp-up) of the measurement cycle is locked to an integral multiple of the mains frequency. This works because the integrator averages the input voltage over the ramp-up period, so any power line fluctuations are averaged to zero over an integral number of cycles.
Where I live the mains frequency is 50Hz, so making tru equal to 20ms (or some integral multiple thereof) will do the trick. For maximum rejection you could use a phase-locked loop to synchronise the ADC clock with the mains.
Obviously dual slope ADC converters are relatively slow compared to other conversion techniques. However, their low cost, high precision, stability and powerline rejection capabilities make them a good choice for multimeters.
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Andrew Levido (andrew.levido@gmail.com) earned a bachelor’s degree in Electrical Engineering in Sydney, Australia, in 1986. He worked for several years in R&D for power electronics and telecommunication companies before moving into management roles. Andrew has maintained a hands-on interest in electronics, particularly embedded systems, power electronics, and control theory in his free time. Over the years he has written a number of articles for various electronics publications and occasionally provides consulting services as time allows.
