Microcontrollers need to be protected from of electrostatic discharge (ESD). You can use the circuit described in this post when you have an application requires a greater degree of ESD protection than what you get from an IC on its I/O pins. Although there are many ESD clamping devices out there, they don’t typically enable you to precisely limit voltage overshoots and undershoots.
Normally, when dealing with a microcontroller or other digital circuit the connections on the device are protected against electrostatic discharge. Nevertheless engineers are 4ever taking special precautions when handling such devices to avoid the risks of ESD: the lab will have an anti-static covering on the floor, and nylon clothes and shoes with soles made of insulating material are avoided. And, in case that is not enough, it is normal to wear an anti-static wrist band when moving devices from their anti-static bags to the anti-static bench surface. But what exactly do we mean when we talk about ESD?
HUMAN BODY MODEL
The first model for static discharge, mentioned as early as the 19thcentury, was the “human body model” (HBM). This takes as its starting point a voltage of up to 40 kV, a body capacitance of a few hundred picofarads, and a (skin) resistance of 1.5 kΩ. We find that even with a static voltage of only 10 kV, as might easily be acquired by walking across an artificial fiber carpet in shoes with synthetic soles, it is possible to discharge through a fingertip at peak currents of up to 20 A! The discharge also happens in a very short period, perhaps measured in nanoseconds.
The HBM was adopted in the electronics industry in the 1970s with the introduction of sensitive JFET devices in space applications. The components were tested using a simple RC circuit like the one shown in Figure 1. The discharge current depends only on the resistance in the circuit, and the damped discharge curve is largely free of oscillation and is accurately reproducible.
Figure 1—Standard test circuit and current waveform for the human body model
There are also other models that deal with discharge through a sensitive component, for example when a low-resistance electrical connection is made between two devices (the “machine model,” or MM), or when a static charge present on the device itself is discharged (the “charged device model,” or CDM)…
ESD CLAMP CIRCUITS
Figure 2 shows the typical protection circuitry provided on a microcontroller’s I/O port. This example is from an Atmel ATmega. Other microcontrollers and logic devices use similar arrangements. Two bipolar protection diodes conduct discharge currents that could cause undershoots or overshoots to one of the supply rails, either VCC or ground. However, the diodes take about 6 ns before they conduct fully.
Figure 2—Typical ESD protection circuit, as found in an Atmel microcontroller
Since ESD transients can sometimes be considerably shorter than this, it is possible that the CMOS circuit structures will be damaged long before the diodes spring into action. The parasitic capacitance of the pin is around 6 pF, and this is quickly charged up by the energy in the electrostatic discharge. Unfortunately, we cannot increase this capacitance without increasing the impedance of the pin, which is not desirable.
Standard ESD protection circuits like this one are designed to meet the particular requirements set by the ESD Association. However, it is becoming apparent that the traditional models are not appropriate for modern applications. Recent efforts have been directed toward developing a new “system level model” (SLM), which takes into account the different aspects of the older models. This model employs two stored charges that are discharged in different ways, creating a high-amplitude current pulse that decays very quickly plus a low-amplitude pulse that dies away more slowly. The energy transferred in a discharge under the SLM can be very much higher than that in the traditional models (Figure 3).
Figure 3—Current waveform under the system-level model
It is readily apparent that the conventional I/O pin circuitry on the IC is not sufficient to provide ESD protection under this model. Also, the continuing industry pressure to make smaller and more complex structures makes it very difficult for design engineers even to maintain current levels of ESD protection, let alone improve on them. In other words: the silicon area needed to provide ESD protection in accordance with the SLM is simply not available! For this reason, external ESD clamp circuits are becoming more relevant. If a component provides only a low level of ESD protection (or even none at all) it is possible to add such a circuit at the points most at risk. The clamp circuits usually use so-called transient suppression diodes (transils or tranzorbs) which, like Zener diodes, start to conduct at a specified threshold voltage. However, unlike Zener diodes, they react quickly and can withstand much higher current transients. There are many variations on the circuit design, but none has exceptional performance and none offers precise clamping of voltage undershoots and overshoots.
STATE-OF-THE-ART ESD CLAMPING
If we are in the lucky position of not having to worry about the last cent of materials cost or the last square millimeter of board area, we can easily create a state-of-the-art active ESD protection circuit from discrete components (Figure 4).
Figure 4—This protection circuit clamps voltage transients outside defined upper and lower thresholds
The transistor circuit forms a kind of regulated voltage divider. The current through the two resistors R2 and R3 is such that the voltages across them are just enough that transistors T1 and T4 start to conduct and T2 and T3 are just short of saturation. So we have one base-emitter voltage (about 600 mV) across each of these two resistors, which means in turn that the emitters of T2 and T3 are 600 mV below VCC and above ground respectively. The circuit as shown is suitable for a 5 V supply; R1 can be changed to suit supplies of 3.3 V or 2.7 V if needed.
What is the point of this complexity? If the I/O pin is high (at +5 V) the upper 1N4148 switching diode will conduct fully as its cathode is at only 4.4 V. If a positive voltage transient should occur it will be conducted by the 1N4148, without switching delay, to the positive rail by 1N5817 Schottky diode D2, which acts quickly and has a low forward voltage. The same thing happens with polarities reversed when a negative voltage transient (below ground) occurs. Hence the digital inputs and outputs are protected against voltage excursions outside the range of the supply rails. In addition, voltage peaks are limited by the use of suppression inductors. The Murata BLM series inductor presents a relatively high impedance to signals in the 100 MHz range and so can significantly reduce the level of transients.
Although the approach we have described works well with digital levels, it is not suitable for use with signals destined for the analog-to-digital converter (ADC) on a microcontroller. In this case a reverse-biased diode between the signal and each supply rail is required to clamp overshoots and undershoots, with a pair of 10 kΩ series resistors to limit the transient current.
The series-connected capacitors C2 and C3 present a low-impedance path for transients between VCC and ground, and hence spikes on the supply rails will also be conducted away.—P. Kruger
RESOURCES
www.teseq.de/de/de/service_support/technical_information/01_Transient_ immunity_testing_e.pdf
www.ti.com/lit/sg/sszb130b/sszb130b.pdf
www.semtech.com/circuit-protection/esd-protection/
www.murata.com/products/emc/basic/feature/bl_intro.html
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