Test Your EQ (Engineering Quotient)

EQ #9

Why do manufacturers specify setup and hold times for flip-flops?

For simplicity, let’s consider a D-type flip-flop, with one clock input “C,” one data input “D,” and one output “Q.” The D input is a voltage that is a function of time. For any given instance of this flip-flop, there is a point for each clock edge in a two-dimensional space, defined in terms of voltage and time relative to the clock edge. If the D input value passes through this point, it will result in the flip-flop going into a metastable state for some indefinite amount of time.
The specific position of this point varies with manufacturing tolerances as well as specific operating conditions such as temperature and supply voltage. Therefore, the manufacturer cannot give you a specific location for this point, and must instead describe a “window” in which the point is expected (with high probability) to exist. The window is described in the voltage dimension in terms of VIL and VIH, and in the time dimension in terms of TSU and TH. As long as all D input transitions are kept out of this window, the flip-flop is guaranteed not to go metastable.

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EQ #9

by Circuit Cellar Staff time to read: 1 min