How many NAND gates would it take to implement the following translation table? There are five inputs and eight outputs. You may consider an inverter to be a one-input NAND gate.
Inputs Outputs
ABCDE FGHIJKLM
11111→00001111
01111→00000011
00111→00000000
00011→10000011
00001→10001111
First of all, note that there are really only four inputs and three unique outputs for this function, since input E is always 1 and outputs GHI are always 0. The only real outputs are F, plus the groups JK and LM.
Since the other 27 input combinations haven’t been specified, we can take the output values associated with all of them as “don’t care”.
The output F is simply the inversion of input C.
The output JK is high only when A is high or D is low.
The output LM is high except when B is low and C is high.
Therefore, the entire function can be realized with a total of five gates:
