Test Your EQ (Engineering Quotient)

EQ #55

Tom, an FPGA designer, is helping out on a system that handles standard-definition digital video at 27 MHz and stores it into an SDRAM that runs at 200 MHz. He discovered the following logic in the FPGA (see Figure 1).

Figure 1

Let’s see if we can work out what it does. To start with, what is the output of the XOR gate in?

When the 27 MHz clock goes from low to high, the first flip-flop changes state. Let’s say that its output goes goes from low to high as well.

Then, when the clock goes from high to low, the second flip-flop’s output will become the same as the first.

On the next rising edge of the clock, the first flip-flop will change again, this time from high to low, and on the next falling edge, the second one will follow suit.

Putting it another way, following each rising edge of the clock, the two flip-flops are different, and following each falling edge, they’re the same. Since we’re feeding them into an XOR gate, the output of the gate will be high following the rising edge of the clock, and low following the falling edge. In other words, the output of the XOR gate is a replica of the clock signal itself!

Why is this necessary?

In many FPGA architectures, clock signals are automatically assigned to special clock routing resources, which are different from, and kept separate from the routing resources used for “ordinary” signals. The tools actually discourage (or even prevent) you from using a clock as an input to a gate or to any input of a flip-flop other than the clock input.

Therefore, when you need to pass a clock into another timing domain as a signal, it becomes necessary to generate an ordinary signal that is a replica of the clock. This is one way to accomplish that.

What is the output of the AND gate?

The three flip-flops in the 200-MHz domain have a delayed versions of the (replica) 27-MHz clock signal. The first two function as a conventional synchronizer to minimize the effects of metastability. The third one, along with the AND gate, functions as an edge detector, generating a one-clock pulse in the 200-MHz clock domain following each rising edge of the 27-MHz clock.

This pulse might be used, for example, to initiate a write request in the SDRAM for each word of video data.


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Tom decided to verify the operation of this circuit in his logic simulator, but immediately ran into a problem. What was the problem, and what could be added to the circuit to make simulation possible?

There is a subtle problem here for a simulator: All of the flip-flops start out in the “unknown” state, and feeding that back (inverted) to the first flip-flop leaves it in an unknown state. The entire simulation will never get out of the unknown state, even though we can reason that it doesn’t matter which actual state the first flip-flop starts out in — the output of the XOR gate will be known after one full clock cycle.

To fix this, it is necessary to explicitly reset the first flip-flop at the beginning of the simulation, and then the rest of the circuit will simulate normally.

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EQ #55

by Circuit Cellar Staff time to read: 2 min