Given a microprocessor that has hardware support for just one level of priority for interrupts, what is the basic scheme for implementing software interrupt priorities? Answer In normal operation, all of the interrupt sources are enabled, along with the processor's global interrupt mask. When an interrupt occurs, the global interrupt mask is disabled and the "master" ISR is entered. This code must (quickly) determine which interrupt occurred, disable that interrupt and all lower-priority interrupts at their sources, and then reenable the global interrupt mask before jumping to the ISR for that interrupt. This can often be facilitated by precomputing a table of interrupt masks for each priority level.