Can a metastable state persist in a flip-flop for more than one clock period?
No. Each new clock edge represents a fresh decision, so any state from a previous clock edge, including a metastable state, is erased.
The only way to have a given flip-flop in a metastable state for multiple clock periods is to create a new metastable state at each clock edge. In other words, the D input would have to be changing on every clock edge.
It is a fundamental principle in the design of asynchronous interfaces—such as UARTs—that input states must persist for at least two sampling clocks. In fact, most modern UARTs use a 16× clock.
That’s not to say that a metastable state can’t propagate down a chain of continuously-clocked flip-flops, but the probability of each successive flip-flop in the chain going metastable decreases exponentially.
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