Open ISA Era Is Here
As a free and open instruction set architecture, RISC-V has shaken things up in the processor realm by offering an ISA that everyone can use without paying a license fee. Processor, SoC, IP and tool vendors have been rolling out a steady stream of products based on RISC-V.
If you were following the processor wars of the early ‘90s, you’ll remember there was a lot of press coverage (from myself included) about RISC (reduced instruction set computing) versus CISC (complex instruction set computing) microprocessor architectures. Fast forward to today and those differences have grown irrelevant—and pretty much all processor instruction set architectures (ISA) became complex.
In recent years, the term RISC is back again in the form of RISC-V. In an industry dominated by ubiquitous architectures such as Arm and the x86 from Intel and AMD, RISC-V has come along and shaken things up by using a new and different encoding scheme created to be free and open so that everyone can use it without paying license fee. In keeping with its RISC name, the RISC-V ISA is simple and compact, but its extensibility is equally important. The RISC-V specification enables custom instruction extensions to facilitate the design of Domain-Specific Architectures (DSAs). These are important for applications such as AI, ADAS, AR/VR, machine learning (ML) and others.
Over the past 12 months, so much has been happening in RISC-V that it all can’t be covered in one article. Here, we’ll look at several of the significant developments in RISC-V over the past year, including from tool vendors, RISC-V core developers and supporting products.
RISC-V BASED FPGA DEV KIT
For its part, Microchip Technology was early to embrace the RISC-V phenomenon via is Polarfire FPGA product line. A year ago, the company introduced its Icicle Development Kit for PolarFire (SoC) FPGAs. System designers who want to deploy a programmable RISC-V-based SOC FPGA can begin development and evaluate the broad network of RISC-V ecosystem products such as real-time operating systems (RTOS), debuggers, compilers, system-on-modules (SOMs) and security solutions. The kit is an enabler for the “Mi-V RISC-V Partner Ecosystem”—a comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support RISC-V designs.
Microchip’s Icicle Kit for PolarFire SoC and Mi-V ecosystem includes a RISC-V processor complex from SiFive and embedded trace macro from UltraSoC. Also included are development tools from AdaCore, Green Hills Software, Mentor (now Siemens) and Wind River. Commercial RTOS solutions such as Nucleus and VxWorks are complemented by Microchip’s Linux and bare-metal solutions. Middleware from AdaCore, DornerWorks, Hex Five, Veridify Security and wolfSSL are included as well.
The Icicle Kit is centered around a 250K logic element (LE) PolarFire SoC device and includes a PCIe connector, mikroBUS socket, dual RJ45 connector, Micro-USB connector, CAN bus connector, Raspberry Pi header, JTAG port and SD Card interfaces, which allow developers a full-featured platform for development (Figure 1). The board is supported by Microchip’s fully designed, validated and tested power management and clocking devices, an Ethernet PHY (VSC8662XIC), USB controller (USB3340-EZK-TR) and current sensors (PAC1934T-I/JQ). Microchip says its Icicle Kit for PolarFire SoC FPGAs is well suited for smart embedded imaging, IoT, industrial automation, defense, automotive and communication applications.
HIGH-PERFORMANCE RISC-V CORE
At the center of the RISC-V game is SiFive, a provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the open RISC-V instruction set architecture specification. SiFive was founded by the inventors of RISC-V. Among its significant rollouts this year was in June with the debut of its two new processor cores, the P270, SiFive’s first Linux capable processor with full support for the RISC-V vector extension v1.0 rc, and the SiFive Performance P550 core, SiFive’s highest performance processor to date.
The new SiFive Performance P550 delivers a SPECInt 2006 score of 8.65/GHz, making it the highest performance RISC-V processor available today, and comparable to existing proprietary solutions in the application processor space. Interestingly, Intel worked as a lead development partner with SiFive on the P550, building a processor on Intel’s 7nm Horse Creek platform. “By combining Intel’s leading-edge interface IP, such as DDR and PCIe with SiFive’s highest performance processor, Horse Creek will provide a valuable and expandable development vehicle for cutting-edge RISC-V applications,” said Amber Huffman, Intel Fellow and CTO of IP engineering group at Intel.
The SiFive Performance P550 features a 13-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GC ISA (Figure 2). Evolved from the previously announced SiFive U84 microarchitecture, Performance P550 scales up to four-core complex configurations that use a similar amount of area as a single Arm Cortex-A75 while delivering a significant performance-per-area advantage.
The SiFive Performance P270 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA. With full support for the RISC-V Vector Extension v 1.0RC, and combined with SiFive Recode, which translates existing SIMD software from popular legacy architectures to RISC-V Vector assembly code, the SiFive Performance P270 is an ideal replacement for dated SIMD architectures. The new SiFive Performance family joins the previously announced SiFive Intelligence family that is focused on AI and ML applications, and the broadly adopted SiFive Essential family of configurable cores that includes the U/S/E-Series of 64-bit and 32-bit processors.
WIRELESS RISC-V SOC
From the embedded processor space, Espressif Systems has been particularly ahead of the game with RISC-V based products. Its most recent RISC-V offering, announced in late August, was its ESP32-H2 SoC with IEEE 802.15.4 and Bluetooth 5 (LE) connectivity, operable in the 2.4GHz band (Figure 3). This SoC comes with an integrated DC-DC converter that enables ultra-low-power, energy-efficient operation. Espressif says that the Bluetooth 5 subsystem has been designed exclusively by its own engineering team. Due to a change in its product planning, the ESP32-H2 is supporting Bluetooth 5 (LE) radio in the place of previously announced Bluetooth 5.2 (LE) radio.
The ESP32-H2 combines two important connectivity technologies. IEEE 802.15.4 radio connectivity has been important to the supported mesh architecture with low power consumption. The availability of Thread and Zigbee protocols address a variety of application use cases. BLE supports point-to-point, broadcast and mesh communication topologies, while it also enables a direct communication between the smartphone and the device.
The combined availability of IEEE 802.15.4 and Bluetooth LE connectivity enables building devices for the upcoming Matter protocol that intends to bring interoperability for Smart-Home devices. With ESP32-H2 and other SoCs in its portfolio, Espressif can offer the full spectrum of Matter protocol solutions for endpoints with Wi-Fi or Thread connectivity, as well as for border router implementations using a combination of SoCs.
ESP32-H2 has a single-core, 32-bit RISC-V MCU that can be clocked up to 96MHz. It has a 256KB SRAM and works with external flash. It has 26 programmable GPIOs with support for ADC, SPI, UART, I2C, I2S, RMT, GDMA and PWM. The ESP32-H2 facilitates building secure connected devices through hardware security features, such as ECC-based secure boot, AES-128/256-XTS-based flash encryption, digital signature and an HMAC peripheral for identity protection, as well as cryptographic accelerators for improved performance.
ESP32-H2 will support Thread version 1.x and Zigbee 3.x. Espressif, as an active member of CSA, will continue to develop and support the Matter protocol on ESP32-H2 for as long as the standard progresses. ESP32-H2 will be supported through Espressif’s mature IoT Development Framework (ESP-IDF), so that customers can benefit from their familiarity with the company’s field-proven platform that already powers millions of connected devices.
PARTNERSHIPS FOR AUTOMOTIVE
Technology partnerships have become a critical linchpin for moving RISC-V technology forward over the past year. For example, in April Renesas Electronics teamed up with SiFive for a strategic partnership to jointly develop next-generation, high-end RISC-V solutions for automotive applications. The partnership also includes SiFive licensing the use of its RISC-V core IP portfolio to Renesas (Figure 4).
Renesas provides automotive solutions including ADAS, Autonomous Driving (AD), Electric Vehicles (EV), and Connected Gateway (CoGW) to automotive system developers worldwide—including its microcontrollers (MCUs) and system-on-chips (SoCs), as well as analog and power products. Renesas says it is exploring the use of next-generation, high-performance RISC-V cores optimized for automotive applications to expand high-end SoC and MCU development capabilities to continue providing innovative and trusted automotive solutions to customers worldwide.
A year ago, Renesas inked a technology IP cooperation with Andes Technology, an advanced supplier of RISC-V based embedded CPU cores and associated SoC development environment. Renesas selected Andes Technology’s AndesCore IP 32-bit RISC-V CPU cores to embed into its new application-specific standard products.
POPULAR OPEN PROCESSOR IP
In many ways, it’s still early days for the RISC-V phenomenon. “There has been quite a lot of opinions on the merits and/or drawbacks of RISC-V, but it is a fact that RISC-V has gained way more traction than any previous attempt at defining ‘open’ processor IP,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “It is too early to say that RISC-V in embedded is a runaway success, but it is clear that it is making inroads into specific use case areas, like storage, and end-point machine learning. There’s also an early trend in using the RISC-V ISA for helper cores on bigger SoC systems, where the RISC-V core is not visible to the end user. It’s probably safe to say that RISC-V is here to stay, but in the end it’s the market that will decide how big it will be.”
Holmberg says that providing embedded software for RISC-V processors is not very different from providing software for any other processor or MCU, but there are some challenges. “Because the ecosystem is innovating fast, the goal posts tend to move fast as well. It can be a bit of a challenge to keep up with new and emerging standards that are in various phases of creation and ratification,” he says.
For its part, IAR Systems provides a Functional Safety edition of its development toolchain IAR Embedded Workbench for RISC-V (Figure 5), which is certified for safety-critical development by TÜV SÜD according to 10 different industry standards. The tools are delivered in a feature-frozen version and actively supported as long as there are customers with active support agreements for that particular version. New certified versions are released when it’s warranted by new features and functionality
RUNTIME TOOL SUPPORT
Tool support for RISC-V based processors continues to ramp up. In August, SEGGER Microcontroller announced that Haawking Technology, a specialist provider of RISC-V-based DSPs, licensed SEGGER’s emRun for RISC-V Runtime Library for distribution with its compiler tools for HX2000 series chips (Figure 6). emRun is a complete C runtime library for use with any toolchain. Written from the ground up specifically for embedded devices, emRun is designed to provide high chip performance with the smallest possible footprint. emRun for RISC-V is assembly optimized for RISC-V, resulting in unrivaled performance and code size on RISC-V devices.
In many cases, the reduced code size makes it possible to use smaller MCUs and less on-chip memory, says SEGGER. This can result in significant cost savings, especially for devices built in large quantities for the mass market. The increase in performance leads to better products with faster reaction times and lower power consumption. emRun is part of SEGGER’s Embedded Studio IDE, which can also be used to easily evaluate emRun.
The HX2000 series is a real-time industrial control DSP based on the RISC-V instruction set, which integrates a high-performance core and application peripherals. It can be used in industrial control, motor drive, digital power supply, new energy and other fields. Within the HX2000 series, Haawking has released the HXS320F2802X and HXS320F2803X subseries into mass production for customer applications. The high performance HXS320F2833X, featuring Haawking’s H28x 32-bit RISC-V core and Harvard bus architecture, is soon to be introduced.
In a similar announcement, back in June SEGGER announced that its J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out of the box. SEGGER’s J-Link debug probe supports RISC-V debug on Codasip’s processor cores. Furthermore, J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries are perfect for minimizing code size.
RTOS SUPPORT FOR RISC-V
Among the companies providing RTOS support for RISC-V platforms is Green Hills Software. Late last year, the company announced the availability of its safety certifiable µ-velOSity real-time operating system (RTOS) for RISC-V (Figure 7). Commercially deployed since 2006, the Green Hills µ-velOSity RTOS’ small footprint, fast-boot and hard real-time responsiveness has provided a solid software foundation for millions of resource-constrained systems. These cover a wide range of deployed IoT applications such as infusion pumps, disk drive controllers, wireless sensors, critical battery management systems, high speed communication modules, and automotive/industrial automation actuators.
Today’s IoT edge designs are increasing their use of RISC-V to execute time- and mission-critical software applications, often in SoCs where the RISC-V cores are combined with Arm or Intel CPUs on a single SoC, says Green Hills. These heterogeneous mixed-core platforms are challenging to debug and optimize, often leading to developer productivity issues that negatively impact product release schedules.
The combination of Green Hills Software’s µ-velOSity RTOS, middleware, hardware JTAG probe, MULTI development tools provides a single integrated development environment that is purpose-built for debug and optimization of heterogeneous processor SoC designs where the RISC-V core is either the main general-purpose CPU or is a secondary special-purpose acceleration core alongside the CPU.
The µ-velOSity RTOS’ simple, intuitive API for RISC-V together with its integrated middleware saves significant development time, says the company. When combined with the comprehensive, safety-certified, OS-agnostic MULTI development tools, developer productivity is increased. Key advantages of MULTI include a single dashboard to view the debugging of heterogenous cores in the SoC, kernel aware debugging, record-setting C/C++ compilers, MISRA-C adherence, and integrated code quality tools for stack performance and run-time errors.
BOARDS SPORTING RISC-V PROCESSORS
Over the past 12 months, numerous board-level products have been under development based on RISC-V processors. Several of these come from the open-spec SBC community and are still to be released. In July, Aldec extended its TySOM family of embedded prototyping boards with the introduction of TySOM-M-MPFS250—its first in a planned series to feature Microchip’s PolarFire SoC FPGA MPFS250T-FCG1152 and the first to have dual FMC mezzanine connectivity (Figure 8). As discussed earlier, the PolarFire SoC FPGA provides a coherent RISC-V CPU cluster and a deterministic L2 memory subsystem. This makes it capable of running Linux and real-time applications.
In terms of board memory, The TySOM-M-MPFS250 is equipped with 2GB DDR4 with ECC (listed as 16Gb MSS DDR4 x36) for the Linux/RISC-V block and 2GB DDR4 (16Gb FPGA DDR4 x32) for the FPGA. There is also a 64Kb EEPROM, some SPI flash, an empty eMMC socket and a microSD slot. The announcement also mentions the presence of LSRAM, uPROM and uRAM linked to the FPGA.
The I/O linked to the Linux-driven RISC-V cores include 2x GbE ports, mini-USB 2.0 and mini-USB serial console ports, and temperature, voltage, current and accelerometer sensors. On the FPGA side you get HDMI, CAN, 2x FMC (HPC, LPC) and a VITA 57.1 compliant PMOD connector. The FPGA block also controls PCIe x4 Gen2 root, 4x user switches and 4x LEDs.
The board’s ability to connect to two FMC daughter cards means it can be used in virtually any industry sector without having to develop custom hardware. Aldec say the TySOM-M series can accommodate larger PolarFire SoC FPGAs when they become available, and that the boards for prototyping designs targeting those devices would be available shortly after.
Aldec | www.aldec.com
Espressif Systems | www.espressif.com
Green Hills Software | www.ghs.com
IAR Systems | www.iar.com
Microchip Technology | www.microchip.com
Renesas Electronics | www.renesas.com
SEGGER Microcontroller | www.segger.com
SiFive | www.sifive.com
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • OCTOBER 2021 #375 – Get a PDF of the issueSponsor this Article
Jeff served as Editor-in-Chief for both LinuxGizmos.com and its sister publication, Circuit Cellar magazine 6/2017—3/2022. In nearly three decades of covering the embedded electronics and computing industry, Jeff has also held senior editorial positions at EE Times, Computer Design, Electronic Design, Embedded Systems Development, and COTS Journal. His knowledge spans a broad range of electronics and computing topics, including CPUs, MCUs, memory, storage, graphics, power supplies, software development, and real-time OSes.