CC Blog Research & Design Hub Tech Trends

Open ISA RISC-V

Written by Stephen Vicinanza

Cements Its Place in the Semiconductor Universe

RISC-V, the open-source Instruction Set Architecture (ISA) that was thought to have no real chance of becoming a standard in the semiconductor market, now has 14% of the global processor market. This astounding accomplishment is due to the exceptional teams RISC-V employs. We look back over the company’s outstanding year and its advancements in the industry as well as those of its sister organizations, especially SiFive. Its journey is one bordered with skepticism but paved with remarkable success.

  • What is open ISA RISC-V?
  • What has led to the rise of RISC-V?
  • What are the advantages to RISC-V?
  • RISC-V

The reduced instruction set computer (RISC) is derived from the Berkley RISC project, starting from the IBM 801 project in the early 1980s. It grew over time to eventually be adopted by most of the semiconductor industry. The RISC-V project was a collaboration between Krste Asanovic and David Patterson, who led the Berkley RISC project, as well as a group of graduate students at the University of California, Berkley. It was originally meant to be a short three-month summer project. As the name indicates, it is the fifth generation of a long series of cooperative RISC-focused research projects.

The RISC-V Foundation was formed in 2015, to own, maintain, and publish the intellectual properties related to the RISC-V Instruction Set Architecture (ISA). When the foundation was formed, the original authors and owners gave up their rights to the foundation. In late 2019 the foundation moved to Switzerland, and in early 2020 renamed itself RISC-V International.

The ISA to date is still a modular design, and its standard extensions are designed to work with the standard bases and with each other without conflict (Figure 1).

Since the move to Switzerland and the renaming of the foundation to RISC-V International, the organization has gone through a substantial transformation. It is abundantly clear that RISC-V is developing into a major ISA, capturing at least 14% of the semiconductor market in just the last two years.

Semico Research reported RISC-V’s SIP market revenue would grow by 36% from 2021 over 2022. This large movement is thought to be the result of many companies using RISC-V as an alternative to traditional CPU SIP types (Figure 2).

Figure 1
The modular instruction set of the RV32IMAC variant. This is a 32-bit CPU with the Base Integer ISA (RV32I) and the ISA extensions for Integer Multiplication and Division (RV32M), Atomic Instructions (RV32A), and Compressed Instructions (RV32C)
Figure 1
The modular instruction set of the RV32IMAC variant. This is a 32-bit CPU with the Base Integer ISA (RV32I) and the ISA extensions for Integer Multiplication and Division (RV32M), Atomic Instructions (RV32A), and Compressed Instructions (RV32C)
Figure 2
 RISC-V is more than just a core. Design costs at recent nodes. (Courtesy of: Handel Jones IBS)
Figure 2
RISC-V is more than just a core. Design costs at recent nodes. (Courtesy of: Handel Jones IBS)

When costs of design for embedded electronic devices were skyrocketing in 2018, it was suggested that RISC-V lacked cohesive point-to-point comparability to other more traditional CPU SIPs. This was ultimately proven false, as we can see today, with CPU manufacturing giants such as Intel and AMD starting to design around the open ISA of RISC-V.

Industry support has grown enormously from 2019 to 2022, with projections of a compound annual growth rate (CAGR) of well over 160% by 2025 in the automotive industry alone, and an overall market-share CAGR of 209% by 2025.

— ADVERTISMENT—

Advertise Here

MEMBERSHIP

RISC-V is still a membership-based organization and remains a non-profit (Figure 3). Calista Redmond became CEO in 2019, after leading the open infrastructure projects at IBM. The members can vote on changes, and only member organizations can use the trademarked logo.

Figure 3
This graph shows the interconnecting tiers of the RISC-V membership. The above companies are just a small portion of the total members of RISC-V, which includes a wide variety of hardware and software companies from around the world.
Figure 3
This graph shows the interconnecting tiers of the RISC-V membership. The above companies are just a small portion of the total members of RISC-V, which includes a wide variety of hardware and software companies from around the world.

In 2020 membership grew from 200 to 400 organizations, and in 2021 it jumped to more than 1000. Over the next year membership increased to 3,100 organizations across 70 countries.

Member organizations range from Andes Technology, the original premier member organization from Taiwan, to Google, a founding member, to Arduino, Oculus, and the most recent premier member Intel Corp. A long list of other semiconductor, software, and hardware companies are currently members.

Membership means many things at RISC-V International. There are three Tiers:

  • Premier Membership at $250,000 per year, which gives you voting power and a seat on the board of directors. There is a $100,000 per year technical steering committee seat membership that offers voting power, but not a direct seat on the board.
  • Strategic Membership based on the number of employees on an annual basis
    • 5000+ employees—$35,000
    • 500–5000 employees—$15,000
    • Less than 500 employees—$5,000
    • Less than 10 employees and
      organization less than 2 years old—
      $2,000
  • Community Membership—no fee
    • Academic Institutions
    • Non-profits
    • Individuals not representing a legal entity

There are three elected board members from the Strategic Tier, which also has eligibility to lead workgroups and committees. The Community Tier has two elected board representatives—one for the community and one for individuals.

The Tiers share three member benefits:

  • Accelerated development, open-source reduced-risk ratified ISA
  • Participation in workgroups, help in strategy and adoption of advancements
  • A total of six support programs
    • Technical deliverables
    • Compliance
    • Advocacy
    • Marketplace
    • Visibility
    • Learning and Talent

Tier-specific benefits and eligibilities include:

Premier Tier

— ADVERTISMENT—

Advertise Here

  • Commercial use of the RISC-V trademark
  • Member logo and name listed on the website
  • Product or solution highlighted on the RISC-V Exchange
  • Press release announcing Premier Membership
  • Four case studies per year, two blogs per month, two social media spotlights per month
  • Spotlight profile, event sponsorship discount

Strategic Tier

  • Commercial use of the trademark
  • Member logo and name listed on the RISC-V website
  • Product or solution listed on RISC-V Exchange
  • One case study per year, one blog per month, one social media spotlight per month
  • Event sponsorship discount

Community Tier

  • Member logo and name listed on the RISC-V website
  • One case study per year, one blog per quarter, one social media spotlight per quarter
  • Event sponsorship discount

Membership is open year-round, and there are great communication channels available at all levels. Some of the strategic members include Microchip, NXP, Samsung, SiFive, and Siemens, among many others.

In February Intel Corp. joined RISC-V International in a move to cement a relationship between the two companies. With this came the announcement of benefits in addition to the Nios V processors based on the RISC-V ISA that Intel already offered. The Intel Foundry Services (IFS) will sponsor and lead an open-source software development platform. This will enable greater freedom to experiment throughout the RISC-V ecosystem, universities, and consortiums.

MAJOR ADVANCEMENTS SEEM TO BE CONSTANT

With major companies coming on board and the rise of SiFive, the ISA is now assured of a seat at the table of the semiconductor industry giants. SiFive is a premier fabless RISC-V chip manufacturer founded by Krste Asanovic, Yunsup Lee, and Andrew Waterman, three University of California, Berkeley researchers and the designers of RISC-V ISA itself.

The company was founded in 2015, and in August of 2017 Naveed Sherwani was named as CEO. In October of that year, SiFive released its first RISC-V-based 64-bit quad-core CPU, which supported full-featured operating systems (e.g. Linux).

The following year the company acquired Open-Silicon and kept their specialized chip manufacturing capability for ASICs. It also released the HiFive Unleashed, a development board with a 64-bit system-on-a-chip (SoC) containing four U54 cores.

Naveed Sherwani left the company in 2020 and Patrick Little was named CEO. From then on the company was focused on growth by offering an array of product families (see Figure 4). In the latest Series F funding round, SiFive raised an estimated $175 million at a $2.5 billion valuation.

Figure 4
SiFive is developing a RISC-V CPU that can be used in mainstream motherboards to run full-featured Operating Systems such as Linux and Windows.
Figure 4
SiFive is developing a RISC-V CPU that can be used in mainstream motherboards to run full-featured Operating Systems such as Linux and Windows.

There are three families of products at SiFive, all based on the RISC-V open-source ISA. Here are the families of products.

SiFive Performance

The Performance family of processors are designed for a maximum throughput, built to maintain efficiency for varied workloads, such as branch-intensive operating systems and multimedia processes. These processors range from eight-stage, dual-issue, in-order architectures that are equipped with 256-bit vector engines, to advanced out-of-order processors with industry benchmark performance that is best-in-class. The Performance family of processors represents next-generation processing focused on the future of RISC-V compute. They include:

  • Performance P650—high-performance four-issue, out-of-order RICS-V applications processor
  • Performance P550—high-performance application processor
  • Performance P270—Vector application core with high-efficiency performance

SiFive Intelligence

The Intelligence family provides an integrated hardware and software solution, which will accelerate ML and AI applications with the SiFive AI ISA extensions and the RISC-V vector Extensions, including:

  • Intelligence X280—512-bit wide RVV, multi-core and Linux-capable, and intelligence extensions

SiFive Essential

There are three families of cores at SiFive, E, S and U families. Figure 5 shows the Essential family’s six performance-level series As.

— ADVERTISMENT—

Advertise Here

Figure 5
The mix and match development board represents the various ways S cores and U cores can be matched together in different design platforms.
Figure 5
The mix and match development board represents the various ways S cores and U cores can be matched together in different design platforms.

The company has seen great growth in the first three quarters of this year. In automotive technologies, Samsung is using the SiFive RISC-V cores for its SoCs and 5G applications. In Samsung’s announcement pertaining to this, it was optimistic about SiFive longevity in the markets. It cited the fact that RISC-V comes with no royalties attached, and when orders reach the hundred million mark the company would see some welcome cost savings.

So does all this mean RISC-V and SiFive will eventually dominate the semiconductor markets? At the moment, that’s where the company and the foundation seem to be headed.

RISC-V DEVICES AND HOW THEY SPELL SUCCESS

This year Intel Corp. invested in RISC-V and will be manufacturing IPs based on the RISC-V open-source ISA. It had already been offering the Nios V processor, and its investment in RISC-V’s growth is a clear sign that the giant has great confidence in
RISC-V’s ability to meet market demand. Intel is putting up $1 billion in the initiative to develop RISC-V chips and processors.

RISC-V CEO Calista Redmond believes in the open model of society, and that “massive investment in open source has the power to change the course of history.” She stated that “open collaboration in RISC-V has already ignited a profound shift in the semiconductor industry, and [the RISC-V-Intel] partnership will accelerate innovation in open computing.”

This level of cooperation and collaboration means a big change in everyone’s game. It will ignite the fear of losses on all sides. But the innovation and advancements of an open-source ISA backed by the might of a colossus such as Intel will drive the industry toward open source.

There are a reported 10 billion RISC-V chips in circulation right now. Many of them are in cloud-native technologies, part of cloud servers and the IoT sector. High-performance computers (HPCs), AI, and Edge computing is also seeing a great deal of play for the open-source ISA. But already companies are using the RISC-V processors in laptops, desktop computers, and data centers as general-purpose processors. These processors are running fully-featured operating systems like distributions of Linux.

Western Digital and Seagate are implementing RISC-V in storage solutions for data-centric and security-critical applications. Many of these solutions are next-generation technologies in the storage and retrieval of large stores of data.

Mainstream media has focused on where the billions of chips that RISC-V has sold are located. This is something of a red herring, as those chips are being held by companies for distribution in systems scheduled for release later this year. Some of those chips are being developed by LeapFive, a computer component company. Also known as Yuefang Technology, LeapFive was founded by the former Google CTO Jiang Zhaohui. The company is preparing to mass produce RISC-V-based chips to meet demand in high-performance logistics, secure computing, and electricity.

The announcement prefaced the company’s desire to compete on the world stage against the x86 and Arm ecosystems. This is a tall order, but LeapFive’s RISC-V CPU NB2 has been shown to readily compete with Arm’s Cortex A55 and A72 chips.

The NB2 comes with an onboard GPU, NPU, and DSP, making it handy for delivering a full-featured Linux system.

As seen in Figure 6, the basic specifications include:

  • Quad RISC-V cores—GPU, NPU, DSP
  • I2C, I2S x4
  • ADC x4, PWM x6
  • SPI x4
  • UARTT2, UART7
  • USB 2.0, USB 2.0 x2,
  • USB 3.0
  • JTAG
  • eMMC 5.1
  • QSPI
  • LPDDR4, LPDDR4X, DDR4
  • SDMMC
  • SDIO
  • UART1
  • MIPI, LVDSx2

The mass production of a RISC-V-based processor set seems to confirm that the company wasn’t exaggerating how prolific RISC-V was and just how far it would go. It seems a certainty at this point that the ISA is being used throughout the world.

Intel’s Foundry Services will manufacture RISC-V cores for Andes technologies, Ventana MicroSystems, Esperanto Technologies, and SiFive (Figure 7). All are delivering high-performance RISC-V chips.

Figure 7
The Cleanroom at Intel's plant is designed to fabricate the RISC-V CPUs used by SiFive, Andes Technology, and many more.
Figure 7
The Cleanroom at Intel’s plant is designed to fabricate the RISC-V CPUs used by SiFive, Andes Technology, and many more.

Still, questions remain as to who will have access to this technology. China and the USA are in a bit of a snit over who will use technologies at Intel’s fab, like EUV. The United States would like to remove access for China. Recent legislation to fund chip manufacturing in the USA has passed and will be a big part of Intel’s war chest in building an $88 billion foundry campus in Ohio.

There are some caveats to the subsidies being dispersed that limit and even outright deny the manufacture of chips for Chinese and Russian sale and use. This could mean problems for some of the foreign companies utilizing RISC-V’s chips. It could cause some diplomatic issues, as well. Still, many are optimistic that RISC-V ISA’s open and free nature will nonetheless secure its future around the world.

Calista Redmond assured Circuit Cellar that there were no geopolitical concerns, and members at RISC-V International were equally distributed around the globe—about 33% of the members are found in each of the US, Europe, and the Asia Pacific region.

Redmond is confident RISC-V will weather political storms and remain open to all who seek to advance technology in a responsible way, paving the way for constant and consistent growth and success.

THE CHANGING MARKETPLACE

In the world of technology and especially computers, a node is usually defined as a physical networked device, such as the kiosks depicted in Figure 8. But nodes can also be the culmination of a distinct technological movement toward a type of device, like the advent of the GUI, and the Nokia cell phone. These advancements produced nodes that are now paradigms in our societies.

Figure 8
In the world of technology and especially computers, a node is usually defined as a physical networked device, such as a kiosk.
Figure 8
In the world of technology and especially computers, a node is usually defined as a physical networked device, such as a kiosk.

The RISC-V phenomenon brings with it a certain motion toward a device that is wholly open-sourced, regulation-compliant, and free from restrictions—not just another fabrication node. Such a device could usher in a technological revolution, as some have said that the more open the source of the vector, the more processing power can be developed. In a nutshell, a device like that has the potential to breakthrough the barrier of Moore’s Law—that the number of transistors in a dense integrated circuit doubles every two years—60 years after it was first asserted.

The RISC-V free model suits the vastly different needs and desires of the development sector in technology. In a general way, the marketplace is transforming at a meteoric rate, while the needs of device and equipment manufacturers are rapidly changing. The one-size-fits-all approach to processors, such as that in the ARM ecosystem, is now being overshadowed by the ability of designers to design the way they want, for any purpose, without restriction, and by the ability to then mass produce those devices without royalty to an ISA company.

In light of new companies, systems manufacturers, and the enormous growth of AI and IoT, an open-source methodology makes even more sense to the big systems companies than to the little ones. While prices are rising for the moment, it seems likely that once supplies return to normal and fabrication is already ramped up prices will drop for off-the-shelf choices in microcontrollers and microprocessors.

Another current trend is a move towardsCPUs that can run fully-featured operating systems. While processors are already out from RISC-V’s SiFive, these are relatively new products that are unknowns for the marketplace. The reliability of the processors, and how they will fair in the main CPUs of Intel and AMD in the x86 space, remains to be seen.

There is still a great deal of skepticism in many arenas and for many reasons. The market has changed. Many of the new systems companies are not trying to sell a product they manufactured but instead piece together a product from component parts they outsourced. The key difference in this process is that now developers can make product specifications as complex or even outrageous as they want.

THE RISC-V DIFFERENCE

RISC-V is not just a set of instructions offered free of charge (Figure 9). There are actually three fundamental differences that encompass the RISC-V ecosystem and which have led to its bullet train rate of success:

  • The architecture
  • The vast amount of open-source implementation of the architecture available to everyone
  • Increasingly availabe cores that surround the processor core

All of the above is backed by tools that help with the implementation and verification of the RISC-V processor.

Figure 9
RISC-V is expanding our horizons in a whole new way, leaving behind the chip giants in favor of new computational worlds.
Figure 9
RISC-V is expanding our horizons in a whole new way, leaving behind the chip giants in favor of new computational worlds.

Simon Davidmann, founder and CEO at Imperas Software, feels RISC-V formed from a solid platform. “Initially it came out of universities, from academics, smart people building a good thing,” he said. “Coming from Berkely in the heart of Silicon Valley, it gained momentum around the area with Berkeley grads. That momentum built quicker than OpenRISC. Academia needed the ISA, and they rode with it until recently.”

There are many new programs and initiatives that have developed out of the RISC-V phenomenon, such as many collaborative groups that have sprung from RISC-V ISA’s foundation of open-source development. These groups bring together industry and academia, like the open cores around the country from many universities, Rocket cores from Berkeley, and ETH Zurich with a pulp platform. Many bring together leaders in the industry, like the CHIPS Alliance, now named Matter, and the OpenHW Group.

Some countries are developing programs that bring together academia and industry for local functionality, like Shakti in India, driven out of IIT Madras. In Israel, the GenPro consortium brings together a university and industry, and even Japan and China have similar programs. All are building open-source RISC-V chips to make them available to for the specific interests of various communities at large.

OPEN SOURCE ISA TO OPEN SOURCE IP, MAYBE

It is a tremendous leap from the Open Source ISA to an open-source processor. There are many groups working on standardizations across the physical construction of processors, but who will regulate the open-source processor?

So far, even RISC-Vs SiFive is using a proprietary processor design. Andy Jaros, Vice President of IP sales and marketing at Flex Logix, says of the temptation to move into fully open-source IPs, “The concept of an open-source IP is very tantalizing because it conjures up the concept of a cost-free IP.”

He goes on to say, “However, open-source is not free. Most companies, unless they want to invest huge resources in IP development, license pre-implements cores from a myriad of IP providers, such as Open5 and Andes, and many others. This saves costs in many areas, development time, verification, software development as well as warranties and indemnification.”

Alluring though the idea of an open-source IP might be, it’s not really functional. There must be some cost to the development of the chip itself, and purchasing a ready-made chip or processor that uses the RISC-V instruction set architecture allows companies to buy chips from multiple sources. By contrast, when developers use Arm ISA, chips must be bought from Arm. Hence RISC-V is competitive with Arm due to the simple fact that more than one manufacturer can negotiate better pricing for RISC-V based chips.

RISC-V IN ORBIT

RISC-V processors have made it into space. Specifically, RISC-V processors are being used on the Trist-R nanosat. The University of Maribor in Slovenia uses a fault tolerant NOEL-V, a RISC-V processor by Cobham Advanced Electronics Solutions (CAES). The processor is implemented in an FPGA. This is a collaboration between CERN and Skylab, a Slovenian company developing space technology and maker of the NANOhpm computer board which is in medium earth orbit (MEO) measuring ionizing radiation.

Ongoing experiments onboard the Trisat-R worked on by ESA and SkyLabs are presenting demonstrations of Radiation Hardening by Design, mitigation techniques to develop protections for high-performance and high-density electronic components which target the development of AI chips in space applications.

This is the first CAES RISC-V processor that has been sent to space acording to the company, which owns and operates the Swedish space design team Gaisler. CAES also works with Lattice Semiconductor, using its Certus-NX-RT and the CertusPro-NX-RT FPGAs.

The NOEL-V is the next generation of the LEON by CAES and meant to lead the way to a RISC-V complement in orbit, running a variety of applications in research and space operations.

CONCLUSIONS

At the beginning of 2018 RISC-V was seen as just another open-source initiative that would develop in a small way across the spectrum of semiconductor realms. There was no doubt at the time it would have a place in the small electronic device markets, but it was believed to be little more than a passing phase like almost all the open RISC-based programs.

Just four years later it has turned into a force that could rival Arm and x86 ecosystems in its speedy ascent to capturing a large share of the chip and processor markets. Its rise in usage across the IoT and AI sectors has unleashed a torrent of buying, preordering, and clamoring for inventory that is certain to last well into the future.

This is due in large part to the very nature of the ISA, being a free and freedom facing architecture. But it’s also a practical business alternative. When Arm is used, then makers must buy Arm chips from Arm. When you want a RISC-V chip, you can buy from the manufacturer with the best price. That equals cost savings, the freedom to design as you please, and no royalties. For this reason perhaps more than any other, RISC-V is ushering in the future with the support and backing of all those who have worked on Open Source ISAs.

This does not mean the death of any ISA, but rather it represents a movement toward standardization and reduced costs over all of the semiconductor worlds. Perhaps with the cementing of a RISC-V open ISA, we can see some progress toward a more varied and feature-rich future in computing. 

RESOURCES
CAES | caes.com
Intel | www.intel.com
LeapFive Technology | www.leapfive.com
RISC-V International | riscv.org
SiFive | www.sifive.com

PUBLISHED IN CIRCUIT CELLAR MAGAZINE • OCTOBER 2022 #387 – Get a PDF of the issue

Keep up-to-date with our FREE Weekly Newsletter!

Don't miss out on upcoming issues of Circuit Cellar.


Note: We’ve made the Dec 2022 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

Would you like to write for Circuit Cellar? We are always accepting articles/posts from the technical community. Get in touch with us and let's discuss your ideas.

Sponsor this Article
+ posts

For the past 8 years, I have been writing about embedded technologies, added to my technical, academic, and medical editorial experience, with companies like Elsevier and Cambridge University Press. I tell people to read what I write, not try to pronounce my last name. I am always available for comments and suggestions you can reach me at product-editor@circuitcellar.com and I promise I will take the time to reach back out to you. I live in the North East with my wonderful family.

Supporting Companies

Upcoming Events


Copyright © KCK Media Corp.
All Rights Reserved

Copyright © 2024 KCK Media Corp.

Open ISA RISC-V

by Stephen Vicinanza time to read: 15 min