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Semiconductor Fundamentals (Part 5)

Written by George Novacek

More on FETs

George continues his article series delving into the fundamentals of semiconductors. In Part 5, he expands his discussion of field effect transistors or FETs. He examines different types of JFETs and MOSFETs, looking at aspects including gate architecture and drain-source I-V characteristics.

Last month we started our discussion of field effect transistors (FETs). Now, let’s expand on the topic. The FET was patented by Julius Edgar Lilienfeld in 1926, preceding the invention of the bipolar junction transistor (BJT) by some two decades. But the FET was never constructed, as the necessary technology wasn’t available at that time.

Let’s start with junction, or JFET structure, as depicted in Figure 1 with its accompanying schematic symbols. JFETs come in two flavors: N-channel and P-channel. The control electrode called gate is a P-N junction forming a diode which must be reverse-biased to achieve the FET’s signature high input impedance. The reverse-biased gate inhibits the movement of electrons or holes, based on whether the channel is of N or P respectively. At zero bias, as shown in Figure 2, the maximum drain-to-source current flows. And because the negative gate bias decreases the drain current, the JFETs are called depletion-mode devices.

FIGURE 1 – Structure of N-channel JFET and schematic symbols of N and P channel
FIGURE 2 – JFET Drain I-V characteristics with VGS a parameter

Analogous to BJTs, FET amplifiers can also be created in three basic configurations: Common source, common gate and common drain—the last also known as a source follower. Figure 2 plots the drain-to-source current ID versus drain-to-source voltage VDS with gate-to-source voltage VGS as a parameter. At some negative VGS called pinch-off voltage VP the drain current will be zero. In the ohmic region the JFET acts as a voltage-controlled resistor:

where RDS is the channel resistance and gm is the FET’s transconductance gain.

JFETs’ dice are smaller than BJTs’. So, the common source JFETs are often used in the long-tailed pair configuration in front-end stages of monolithic op amps. This topology has very high input impedance and good voltage gain. Common gate topology can be seen as the second stage of a cascode amplifier, also analogous to the BJT version with the same advantages and disadvantages. The source follower is frequently an integral part of high resistance sensors—such as the pyroelectric ones—because it matches their high input resistance to a low resistance output.

In saturation the IDSS current shows very little dependence on the drain-to-source voltage. This makes the design of constant current sinks and sources easy (Figure 3). Resistor R adjusts the magnitude of the sink current which, for R = 0 is the maximum saturation current IDSS. To set a lower current the resistor R value is increased. A P-channel JFET operated at opposite polarities forms a constant current source.

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FIGURE 3 – N-channel JFET constant current sink

JFET APPLICATIONS
As shown in Figure 1, JFET is a symmetrical device, so the drain and source terminals are interchangeable. This property makes JFET useful as an analog switch or a voltage-controlled resistor. Applications include volume control, voltage-controlled oscillators, modulators and wherever a variable resistance is needed. Because of their high input impedance and small geometry, FETs also find their use in low noise, high frequency circuits up to about 30GHz.

Figure 4 is a basic N-channel, common source JFET amplifier. When setting up its DC operating point you must remember to keep the gate electrode negatively biased with respect to source. Here the gate is connected to the ground potential VG = 0 and the source electrode’s potential is raised by drain current ID through resistor RS to VS, just as we used to bias triodes. With the working ID established from the JFET I-V diagram, you compute resistor values RS and RD to set VD to approximately (VDD – VS)/2. Of course, you need to know the JFET characteristics—unfortunately, specification sheets I have checked give you very little data—just enough for designing an analog switch, but nothing more. You need to do some measurements of your own.

FIGURE 4 – A common source low frequency amplifier

In the Figure 4 amplifier example I used J110 JFET with RG= 1MΩ, RS = 470Ω and RD = 1kΩ. The DC operating point of this amplifier was VS = 2.3V, VD = 7.15V, VG = 0V and VDD = 12V. To obtain a useful AC gain I bypassed RS with a 100µF capacitor, which resulted in the gain of 23dB (AV ≈14), – 3dB flat from 26Hz to 21MHz.

As mentioned earlier, JFETs come as N-channel and P-channel. The N-channel is doped with donor impurities and, therefore, the current through the channel is negative in the form of electrons. The P-channel is doped with acceptor impurities and, consequently, the current through the channel is positive in the form of holes. Because electrons have higher mobility than holes, N-channel JFETs exhibit greater channel conductivity (lower resistance) than their P-channel counterparts. The N-channel JFET is more efficient and, therefore, while available, P-channel JFETs are not as frequently used.

MOSFETS
The next step is to contemplate the metal-oxide semiconductor field effect transistor or MOSFET. Just like bipolar transistors and JFETs, MOSFETs come as N and P types. Additionally, each type can be an enhancement or depletion, so that makes our MOSFET types. Most digital ICs today—including microprocessors, microcontrollers, storage devices and so on—are made using MOSFET technology. In the ‘70s, purely PMOS or NMOS ICs had been fabricated, but today complementary pairs of the N- and P-channel transistors let us build CMOS devices with high speed and low power consumption.

The main difference between the JFET and the MOSFET is that the MOSFET gate is isolated from the body of the semiconductor by an oxide insulator. Therefore, an extremely high input resistance to the tune of 1,012Ω is obtained. I used such a MOSFET to interface with an ionization chamber that had a cross-current around 1-2nA. Because the gate could be easily destroyed by static electricity discharge, many MOSFETs have an internal diode protection, somewhat degrading the high input resistance.

Figure 5a illustrates the N-channel enhancement MOSFET structure, Figure 5b shows the N-channel depletion mode structure. Notice that MOSFETs have a fourth electrode called body, bulk or substrate. It is generally connected to the source potential. Many MOSFETs have the connection done internally and no lead outside the enclosure. Also notice that the substrate-to-drain and substrate-to-source junctions form intrinsic diodes. With the bulk usually connected to the substrate, the substrate-to-source diode is shorted. But the substrate-to-drain diode is the reason why the MOSFET drain and source are not interchangeable. The diodes are shown in the MOSFET symbols (Figure 6). The P-channel MOSFET’s structure looks the same, just the polarities are reversed. The N-channel enhancement MOSFET, in my experience, is the most prevalent for switching and digital applications.

FIGURE 5 – Cross-section of N-channel enhancement (a) and depletion (b) type MOSFET
FIGURE 6 – Shown here are the symbols of enhancement (a) and depletion (b) type N-channel MOSFETs and enhancement (c) and depletion (d) type P-channel MOSFETs. No bulk terminals are present.

By now MOSFETs have replaced BJTs in many applications, including communications reaching up to the many gigahertz. Dual gate MOSFETs were developed especially for applications as oscillators, mixers, multipliers, amplifiers and so forth in RF, VHF, UHF, microwave and higher frequency ranges. Both gates affect the operation of the device, which could be viewed as two MOSFETs in series. Their respective symbols are shown in Figure 7. Notice the intrinsic diode is not always shown in the MOSFET symbol.

FIGURE 7 – Here are the symbols of dual gate enhancement (a) and depletion (b) type N-channel MOSFETs and dual gate enhancement (c) and depletion (d) type P-channel MOSFETs.

A dual gate MOSFET can form a cascode amplifier overcoming the Miller effect as discussed previously. The Miller effect relates to the impedance between the output and the input, but at high frequencies capacitance is the predominant factor, potentially leading to instability. Biasing Gate 2 (also called the drain gate) at a constant potential, well bypassed to the ground, eliminates the capacitive coupling and thus the Miller effect.

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The I-V characteristic of depletion MOSFETs is similar to that of the JFETs in Figure 2. Enhancement MOSFETs need some minimum gate to source voltage to begin to conduct as seen in Figure 8. Design of an amplifier with enhanced mode MOSFETs is along the same lines as described earlier for JFETs. Just the gate biasing is different. MOSFETs intended for logic switching applications guarantee minimum RDS—in other words, the drain-to-source resistance, often in milliohms, at the gate voltages less than 5V.

FIGURE 8 – Drain–source I-V characteristics of an enhancement type N-channel MOSFET

BUILDING BLOCKS
Some readers may think discussing discrete components unnecessary. Thanks to the availability of many inexpensive integrated circuits (ICs) and system building blocks, circuit design with discrete components is becoming almost an arcane art. But, all that said, transistors are the building blocks of ICs—devices that many make a living designing. And even if IC design is not in your future, understanding their underlying principles can only help with product designs and troubleshooting.

We’ll complete the series next month with a look at power MOSFETs and some nearly exotic components with multiple P-N junctions. 

Go Here to Read Part 1

For detailed article references and additional resources go to: www.circuitcellar.com/article-materials

PUBLISHED IN CIRCUIT CELLAR MAGAZINE • JANUARY 2020 #354 – Get a PDF of the issue


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George Novacek was a retired president of an aerospace company. He was a professional engineer with degrees in Automation and Cybernetics. George’s dissertation project was a design of a portable ECG (electrocardiograph) with wireless interface. George has contributed articles to Circuit Cellar since 1999, penning over 120 articles over the years. George passed away in January 2019. But we are grateful to be able to share with you several articles he left with us to be published.