Coping with Complexities
Printed circuit boards continue to grow more elaborate, with the chips populating them gaining complexity as well. To support these designs, PCB tool vendors are enhancing their software suites to support higher-speed signals, collaborative team designs and many other challenges.
There’s a lot on the plates of today’s PCB design tool providers. As PCBs get ever more complicated, efforts continue to address more facets of the PCB design process while improving basic functions such as automated chip placement and intelligent routing. New versions of PCB tools are addressing high-speed design, multi-board designs, 3D designs, component management, IC-PCB co-design more.
If there’s a theme over the past 12 months for PCB tool enhancements, it’s about systems. New features continue to roll out that treat PCB design in more of a systems context. This means not just PCBs as a physical object within a system, but also the system processes revolving around PCBs, including collaborative team design support and greater integration with PCB analysis and verification solutions.
HIGH-SPEED DESIGN FEATURES
Exemplifying those trends, in December Altium rolled out version 20 of its flagship PCB design software Altium Designer. The new version’s features include a faster schematic editor, high-speed design improvements and enhanced interactive router capabilities enabling faster board design.
Among Altium Designer 20 (AD20)’s enhanced interactive routing features are new “push & shove’’ capabilities that enable routing of complex HDI boards and speed-up design times by over 20%, even for simple PCBs (Figure 1). To support high-speed PCB routing, the tool enables users to efficiently design high- density and high-speed boards using modern SerDes like PCIe 4.0/5.0, USB3.2, 100G Ethernet and parallel buses like DDR3/4/5.
In a multi-board design context, one of the most insidious issues is not just connector alignment, but the correct assignment of signals on the connector pins. When working with standards, this is not as much of a problem because signal assignments are predetermined. But when designing new multi-board systems, the connector pin-to-signal assignment is up to the system designer, and many projects have been derailed because of swapped pins or incorrect connector pin numbering on one of the boards. In a Native 3D Mulit-Board design environment, signals are traced through connections from board-to-board and board-to-cable-to-board, allowing errors to be found and assignment to be fully synchronized across all PCB designs in the system, before prototypes are built (see the Cover image of this issue, Circuit Cellar 360, July 2020).
For applications where high-voltage design is critical—such as spacecraft, high-altitude aircraft and high-tech lasers—AD20 provides new creepage rules that help maintain high-voltage clearances across the PCB surfaces for prevention of electrical arcing hazards for power supply and mixed-signal device designs.
SHARED CANVAS APPROACH
Among the interesting features in the latest version of Cadence’s Allegro software is its Allegro PCB Symphony Team Design Option (Figure 2). It enables collaborative placement, routing, auto-interactive routing, interactive routing and shape design. This lets design teams dedicate their time and efforts to get designs done faster through real-time concurrent design collaboration.
This Allegro option operates as a shared canvas providing a low-overhead environment in which multiple designers can work on the same design, on the same canvas and at the same time without the set-up requirements of a partitioned project. The more routing engineers you add, the faster your team can finish routing.
By connecting multiple PCB designers to a common Allegro PCB layout database, any changes made on their canvases are reflected on the server and seen by other designers, eliminating copy/paste “chaos.” You can bring other team members into a design on a moment’s notice. Join or leave the session at any time, knowing that all design updates have been updated to the master database. Designs are hosted on a network server where multiple designers can access the server and start the concurrent design process. PCB designs can be managed centrally without requiring user intervention.
Many tasks—such as netlist updates, MCAD updates, constraint updates and so forth—frequently interrupt the PCB implementation process. The constraint editing capability in the Allegro PCB Symphony Team Design Option allows a client exclusive access to Constraint Manager while everyone continues their design work concurrently. You can leverage netlist import and MCAD import within the Symphony Team Design Option session without disconnecting team members from the session.
If the shared canvas approach isn’t ideal for your design team, Cadence also provides its Allegro PCB Design Partitioning Option (available separately). It lets designers work on individual design sections exported from a master design. Partitioning a design for layout and editing by several design team members accelerates the time to complete the layout process. Each designer can see all partitioned sections and update the design view for monitoring the status and progress of other users’ sections.
PCB LAYOUT FLEXIBILITY
In March, Mentor announced that the latest release of its Xpedition, VX2.7, was available for download. According to the company, Xpedition VX.2.7 is enhanced with many new features that improve product usability and efficiency as well as improvements in the UI and overall usability. Like other vendors, Mentor has added ideas submitted from users. The new features comprise several aspects including multi-board system design, design creation, schematic capture, simulation, layout, library management, layout and design for manufacturing (DFM). For the purposes of an overview, in this article we’ll look at a couple of those areas.
In terms of layout, the latest release of Xpedition VX.2.7 offers features that span from component placement to sketch planning and beyond. Selection of connections for assignment to a sketch path or sketch plan can now be done by selecting pins. You can also now manually place parts one after the other or with auto-arrange. There’s also a new option while routing nets which allows for pin swapping. This works for single nets and differential pairs. Meander editing in Xpedition VX2.7 (Figure 3) now supports connection points in complex vias to get a consistent user experience with other routing commands.
Xpedition VX2.7 has also enhanced its support for multi-board system design. The association of multiple PCBs to the system design can now be completed with a single check-in of the system design. The algorithm to manage each board’s synchronization states has also been optimized to significantly reduce the time to analyze the design’s synchronization. For large systems, this new process can take minutes off the verification time in checking each board. Also, a new design rule check (DRC) has been created to verify mated connectors. This ensures the mating on the schematic matches the mating in the library.
On the schematic capture side, the VX2.7 version provides improvements to ease-of-use and flexibility. The new release contains multiple usability improvements. Grid options, tab closures, and keyboard shortcuts are enhanced and made simpler. New additions to the Partlister definition files create a report showing which parts in a design have been created using PartQuest. Meanwhile, the software’s designer verify tool now analyzes the schematic-level (and block-level) pin type, rather than only analyzing the symbol pin type. The priority order is: Instance > Block > Symbol. The tool also supports pin type overrides from I/O Optimizer. This enables you to make use of any pin type changes directly from your schematic.
PCB DESIGN VERIFICATION
Mentor’s new VX2.7 version of Xpedition also offers enhancements to PCB design verification. This takes the form of new integration features between Xpedition and Mentor’s design verification (analysis) tool called HyperLynx. HyperLynx is a complete family of analysis tools for high-speed electronic design including electrical design rule checking (DRC/ERC), signal integrity (SI), power integrity (PI) with integrated 2D/2.5D/3D electromagnetic modeling (3D EM).
Users can launch HyperLynx from Xpedition’s EDM (engineering data management) tool suite and manage data from simulation “sand boxes” based on user (Figure 4). Results are also tracked if HyperLynx is launched from within Xpedition’s authoring tools. Users can now also work with HyperLynx versions out of sync with the last two releases of Xpedition. This allows more frequent updates to analysis tools, while maintaining a stable authoring flow longer. Custom FPGA devices can now be modeled automatically for schematic analysis. An online database of Altera and Xilinx FPGA components is available for free to download. This greatly reduces the time it takes to model large, customized components.
In Xpedition VX2.7, you can open your datasheet directly from your schematic analysis project. The datasheet location can be specified directly on the bill of materials (BOM) or in your Designer properties. Analysis of results is made simpler by quickly locating your datasheet for review, says Mentor. Another feature lets you design your BOM for schematic analysis. This new functionality allows you to maintain model assignment connections to parts that have a different part number for schematic analysis.
Among the interesting features in the latest version of CR-8000, Zuken’s 3D PCB and IC tool suite are capabilities for comprehensive system co-design. Called Design Force, these capabilities recognize the interaction between chip, package and board data to reduce complexity, size and cost of the overall system (Figure 5).
In addition to advanced PCB layout capabilities, Design Force provides chip, package and board co-design capabilities to enable real time 3D hierarchical design. This allows design teams to concurrently create any combination of advanced die stacks, packages and PCBs. A multi-board constraint browser lets you view and analyze system level interconnects. Automatic ball assignment lets you optimize complex routing solutions.
Using a single environment, you can do high-speed design with constraint management and signal integrity (SI) and PI power integrity (PI) analysis. The tool’s routing engines can do rapid feasibility studies or detailed redistribution layer (RDL) and bump escape routing of signals, as well as power and ground nets.
Long gone are the old days when just placement and routing were the entire scope of PCB design tools. Both PCB designs themselves and the ICs populating them continue to grow more and more complex. PCB design tool vendors must keep pace with advanced, integrated tool solutions.
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • JULY 2020 #360 – Get a PDF of the issue
Jeff served as Editor-in-Chief for both LinuxGizmos.com and its sister publication, Circuit Cellar magazine 6/2017—3/2022. In nearly three decades of covering the embedded electronics and computing industry, Jeff has also held senior editorial positions at EE Times, Computer Design, Electronic Design, Embedded Systems Development, and COTS Journal. His knowledge spans a broad range of electronics and computing topics, including CPUs, MCUs, memory, storage, graphics, power supplies, software development, and real-time OSes.