Amplifiers in Action
A high-voltage differential probe is a critical piece of test equipment for looking at high-voltage signals. In his article, Andrew describes his design of a high-voltage differential probe with features similar to commercial devices, but at a considerably lower cost. It uses just three op amps in a classic instrumentation amplifier configuration and provides a great exercise in precision analog design.
A high-voltage differential probe is an indispensable piece of test equipment for anyone who wants to examine high voltage signals on a standard oscilloscope and do so safely. For safety reasons, the ground side of your oscilloscope probe is connected directly to mains earth. This means you can only measure earth-referenced signals, or truly floating signals, such as those encountered in battery-powered circuits, where it is possible to connect one part of the circuit to mains earth via the scope.
But what if we want to measure some signals in a mains-referenced circuit such as an off-line switch-mode power supply? The control circuit is typically referenced to the negative side of the rectified mains. This point is certainly not at earth potential. If you were to connect the ground clip of a standard oscilloscope probe to this point, you would create a short directly to earth via your oscilloscope. This would almost certainly damage your oscilloscope and probably destroy the circuit under test.
Incidentally, when I started my career many years ago in the power electronics field, you would routinely see oscilloscopes with the earth wire cut at the mains plug to avoid just this problem. This was—and remains—an extremely dangerous practice, because it meant that the entire oscilloscope would be floating at mains potential. Merely touching the case of the scope could deliver a fatal shock. I even owned a 1970s era oscilloscope with a “ground lift” switch on the back panel to make it more convenient to make the instrument lethal.
Fortunately, there is a safe way to measure high-voltage circuits such as in this example: a differential probe. It has two high-impedance inputs and a single, ground-referenced output. The output is proportional to the difference in voltage between the positive and negative inputs. Any common-mode signal is rejected. In the example of our off-line switcher, we would connect the negative input to the “reference” rail, and the positive input to the point we want to investigate. The output would be proportional to the difference between the two.
While I have owned a commercial differential probe for some years, I find it a little bit inconvenient to use. That’s because it requires a wall-wart power supply that clutters up my benchtop and it is quite chunky. I thought it would be nice to build a differential probe that was reasonably small sized with a rechargeable battery. It has proved to be an interesting exercise in precision analog design, as you will see later.
I wanted specifications similar to commercial units costing $300 or $400, so I started by writing down a few target specifications:
• Basic gain accuracy of better than 1%.
• Input impedance above 1 MΩ with parallel capacitance under 5 pF.
• Input voltage range suitable for measuring 230 V +15% mains, which we have in Australia (let’s say ±400 V). It should be safe to connect to considerably higher voltages
• A bandwidth of at least 25 MHz
• DC and 50/60 Hz common-mode rejection ratio (CMRR) of 60 dB or better (1/1,000)
• More than 3 hours of battery life
In principle, the concept of a differential probe is pretty straightforward: a matched pair of input attenuators followed by a classic three op-amp differential instrumentation amplifier, as shown in Figure 1. You can think of this circuit has having three sections: an attenuator, a buffer stage and a difference amplifier stage. The overall gain of the circuit is given by multiplying the gains of each of these stages as shown in this equation:
I started by choosing the input attenuation ratio to be 1/200, so that the maximum operating voltage of ±400 V will be attenuated to ±2 V—low enough to be within the input common mode range of typical FET input op amps powered from ±5 V rails. Of course, this means smaller signals—such as the gate drive in our notional power supply—will be just a few tens of millivolts after the attenuator. Clearly, we need the following stage to optionally provide some gain when we are looking at small differential signals.
The good news is that the gain of the buffer stage of a classic instrumentation amp such as this can be programmed a single resistor, Rd in Figure 1. If Rd is open circuit, the gain of this stage will be unity, suitable for input signals in the multi-hundred-volt rage. By switching in a resistor Rd we can add an additional range with a gain of perhaps 10, allowing us to sensibly measure differential signals in the tens of volts.
The final stage is the difference amplifier, which converts the differential signal into a single-ended ground-referenced one. I decided to set the gain of this stage to 2, so that the overall differential gain of the instrument would be 1/100 or 1/10, and the maximum output swing is nominally ±4 V which we should be able to achieve with ±5 V rails. Therefore, our full-scale input ranges are ±400 V or ±40 V.
So far, so good. I now had three analog stages to design, plus a power supply. To achieve an overall DC gain accuracy less than 1%, each stage had to have a gain accuracy of about 0.25%. Achieving greater than 60 dB CMMR (common mode rejection ratio) means matching the attenuators and the resistors in the difference amplifier to at least 1 part in 1,000. Achieving a large-signal bandwidth greater than 25 MHz would require some pretty special op amps and careful attention to parasitic capacitances and board layout. I also had to contend with all the usual non-ideal characteristics of op amps such as input offset voltages, input common mode ranges, input bias currents and the like. Sounds like fun, so here I will walk through the design process pretty much as I tackled it.
For this stage, we need a pair of input attenuators capable of safely withstanding mains voltages, with a high input impedance, each with a gain of 1/200 matched to better than 0.1% and with a bandwidth of at least 50 MHz.
I started by selecting the input resistance Ra to be 4 MΩ, made up of a string of four, 1 MΩ, 0.1%, 0.4 W, 1206 SMT resistors in series. Series resistors are required here, since the maximum working voltage of a single resistor of the type I chose is limited to 200 V. A quick check shows power dissipation in this resistor string will not be an issue up to 2.5 kV, so the maximum voltage is limited to 800 V by the resistors’ maximum working voltages. This comfortably exceeds our design requirement of 400 V.
The value of Rb can now be calculated to be 20.1005 kΩ. The schematic in Figure 2 shows this pretty odd value is made up of a string of resistors and a trim-pot. In practice, we can achieve a DC CMRR of better than 120 dB with this arrangement.
Half the trimpot accounts for 50 Ω of the value of Rb. The rest is made up of two 10 kΩ, 0.1% resistors and a 91 Ω, 1% fixed resistor. The 10 kΩ resistors are part of a 4-resistor matched array. This turns out to be a much cheaper way of buying precision resistors than as individual components, though with a limited range of values. As an added bonus, these resistors are matched to each other within 0.05% and track with temperature, because they are in on the same substrate. This helps keep our attenuators matched.
The astute reader will have already observed that this combination of resistors adds up to 20.141 kΩ, not the 20.1005 kΩ mentioned above. This is because we have to take into account the effect of the parallel 10 MΩ resistors (R12 and R15). 10 MΩ in parallel with 20.141 kΩ is bang on 20.1005 kΩ. R12 is associated with op amp offset nulling, discussed later, while R15 is there purely to keep the circuit symmetrical.
We can safely ignore the input impedance of the op amp as we will use an FET input type with an impedance north of 100 GΩ. Similarly, a quick calculation shows that with an approximately 20 kΩ source impedance, we can ignore the op amp input bias current as long as it is less than 50 pA. The diode pairs DP1 and DP2 are there to protect the op amp inputs from any overvoltage making its way through the attenuator. They effectively clip the signal to one diode drop above or below the supply rails.
This is all well and good for DC signals. We have a safe circuit with precise attenuation and great CMRR. But what about the AC behavior? The buffer op amps will have a small but finite input capacitance, as will the protection diodes. This capacitance, with the 4 MΩ input resistance, forms a low-pass filter that will severely attenuate high-frequency signals. According to the datasheets, this combined capacitance of the op amp and protection diodes will be on the order of 4.3 pF. Not much, you might say. But the corner frequency of this low-pass filter will be under 10 kHz.
The answer, of course, is to add some frequency compensation capacitance across the 4 MΩ resistors. The impedance of this and the parasitic capacitance should be in the same ratio as the resistances in the voltage divider. In our case, the compensation capacitors should be 199 times smaller than 4.3 pF. Obviously, this is not practical, so we have to tackle this problem from the other direction. First, let’s choose a reasonable compensation capacitance and calculate the other capacitance.
I chose to use a string of four 10 pF, 500 V, 5%, 1206 SMT capacitors in series. This gives us a compensation capacitance of 2.5 pF and will handle input voltages to 2 kV, comfortably exceeding our ±800 V input limit defined by the resistors. For proper frequency compensation we now need a total capacitance at the input to the buffer op amps of 497.5 pF. In practice, this is made up by the parallel combination of the op amp and diode input capacitance, two fixed capacitors (C9/C10 and C11/C12) and a trimmer capacitor. The trimmer provides a range of adjustment of 461 pF to 524 pF to allow for component tolerances and layout differences. The total capacitance seen at the input terminals is nominally 2.5 pF, since the compensation capacitors will dominate.
Next is the three op amp instrumentation amplifier. This classic circuit has a few very nice features that come in handy for this application. It has very high input impedance, common mode gain of 1 independent of resistor matching, and differential mode gain programmable via just one resistor as already discussed.
The technical requirements for the input op-amps for U1 and U2 are pretty tough. I needed FET inputs for high impedance and low bias current, a very wide large signal bandwidth, a flat response below about 50 MHz, low input offset voltage, ±5 V supply rail supplies and an input common mode range to ±2 V. I chose Analog Devices’ ADA4817, which is expensive at around $10, but fits the bill nicely. It has an input impedance of 500 GΩ in parallel with 1.3 pF, typical input bias current of 2 pA, a large signal bandwidth to 200 MHz, 0.1 dB gain flatness to 60 MHz, a typical offset voltage of 0.4 mV (very low for a FET input op amp) and an input common mode range of -4.2 to 2.2 V with ±5 V rails.
If I only required a gain of 1 for this stage, I could have simply wired these op-amps as non-inverting buffers. Since I wanted to have the option of a gain of 10, I had to close the feedback loop around each op amp with a resistor (R18 in the schematic and Rc in Figure 1). It is a good idea to choose a fairly low value for this resistor, because it will form an RC low-pass filter with the op amp input capacitance—the effect of which will be to increase the gain of the buffer as the frequency rises.
I selected a resistance of 500 Ω, made up from a pair of paralleled 1 kΩ resistors from another precision matched resistor array. This minimizes the effect of gain peaking in the frequency range of interest, but there is still a potential issue at high frequencies that should be addressed. The 510 Ω resistor in series with each op amp’s non-inverting input is the result. It forms another low-pass filter that attenuates the input signal at about the same rate as the low-pass filter in the feedback loop amplifies it. Neat.
With Rc (Figure 1) fixed at 500 Ω, we can easily calculate the value we will need for Rd to achieve a gain of 10 on the high-gain range. This turned out to be the infinitely repeating value of 111.11 Ω. This odd value was easy to create with a parallel combination of 120 Ω and 1.5 kΩ (R20 and R21 in Figure 2). You will note from the schematic that I have specified a 0.1% tolerance for the 120 Ω resistor, but only 1% for the 1.5 kΩ resistor. I could do this because the error in the 120 Ω resistor dominates, and any tighter tolerance on the other resistor is just wasted money. The same applies for the 91 Ω resistors and the trimpot in the input attenuator. This is a trick well worth keeping in mind for your precision designs.
Just as for the input attenuator, I had to provide frequency compensation for the voltage divider formed by Rc and Rd (Figure 1). As before, I selected a nice round value (100 pF) for the capacitors across Rc (R14 and R15 in Figure 2) and calculated that we needed 450 pF across R20 and R21. This is a series connection of 470 pF and 10 nF capacitors.
The final difference amplifier is, by comparison, fairly simple to design. The rejection of any remaining common-mode signal relies on well-matched components, so again I took advantage of low-cost matched resistor arrays for R22 and R23. For this op amp, I could relax the requirements a little compared with U1 and U2. Any input impedance greater than about 5 MΩ and an input capacitance lower than about 5 pF should be fine, because the source impedance is relatively low. Similarly, an input bias current less than 10 µA should be no problem. I needed an input common mode range of ±2 V and an output swing of ±4 V. A lower cost CMOS op amp should suffice here, so one would expect fairly low input offset voltages compared to the FET input op amps used in the previous stage. I did, however, need a pretty good large signal bandwidth.
I chose the LM6611 from Texas Instruments (TI), which has an input impedance of 6 MΩ in parallel with 2.5 pF. Typical input bias current is -6.5 µA. Input common mode range is -5.2 V to +3.8 V, and input offset voltage is typically 74 µV. The output can swing to within 200 mV of the supply rails into a 1 kΩ load. The output is intended to be connected to a standard oscilloscope input, which is typically a 1 MΩ resistance in parallel with a few picofarads of capacitance. The 51 Ω resistor R30 is there to protect the output op amp from inadvertent short circuits.
Calculations show we need ±5 V power rails with a maximum current drain in the order of 80 mA. I chose to use a single cell LiPo battery as the power source, since this could be charged from the standard USB power supplies that have become ubiquitous. An AA-sized (14,500) cell would fit nicely in the case I had in mind. I needed two switch-mode converters—one to step the battery voltage up to +5 V and another to create the -5 V rail. There are a few ways to do this, but I figured I could not be the first person with the need for dual 5 V supplies from a single LiPo cell.
After a few hours on various manufacturer websites, I came across the TPS65133 from TI, which fit the bill perfectly. This nice little chip accepts a 2.9 to 5.0 V input and produces ±5 V rails at up to 250 mA. It is 92% efficient at 100 mA. It requires only a couple of inductors and three low ESR ceramic capacitors. The chip also has a low-voltage shut-down to protect the LiPo cell from over-discharge. I was concerned that there might be a bit too much switching noise on the power rails, so added an LC filter (L3/C29 and L4/C30) between the switcher and the analog circuitry. A green LED (LED2) across the power rails provides user indication that the power is on.
The battery is charged from a Micro B USB connector via a MAX1555 charger from Maxim Integrated. This is a very simple linear charger with two inputs, intended to be used in applications where there is both a USB power source and a DC wall wart. If power is present at the DC input (U4 pin 4), the LiPo cell will be charged at 280 mA. If only the USB source is available (U4 pin 1), charging will be limited to 100 mA, respecting the USB specification. I have configured the circuit so I can connect either of these inputs to the USB connector via R24 and R25. By omitting R24 and loading a 0 Ω resistor in R25, I can choose to use a high-current USB charger for faster charge or, by omitting R25 and loading a 0 Ω resistor in R25, configure the differential probe to be USB compliant and put up with a longer charge cycle. A green LED (LED 1) indicates that the battery is charging. The USB power input is protected by a TVS diode (Z1) and a resettable thermal fuse (F1).
Note that the power switched via SW1A. In the Off/Charge position, the battery is connected to the charger and isolated from the rest of the circuit. In either the x10 or x100 gain position, the battery is connected to the switcher and isolated from the charger. This means it is not possible to both use and charge the probe. This was a deliberate choice on my part to keep the modes completely separate and encourage me to keep my bench as clear as possible.
Testing shows the circuit can achieve 3 hours and 45 minutes of operation on a full charge with the 800 mA-hours LiPo I used. Charging takes a couple of hours on the high-current setting, and about 6 hours on the low-current setting. You could substitute an 18650 cell if you reconfigure the mechanical design, which should more than double both the running and charging times.
I built my probe on a double-sided printed PCB, sized to fit a Hammond Industries 1593X handheld case, measuring 66 W mm x 140 L mm x 28 D mm. Figure 3 shows a view of the case. Two 4 mm banana input sockets protrude through one end of the case, and the BNC output connector and USB Mini-B connectors protrude through the other end. The power/range switch is on the top of the case, which also houses two off-the-shelf light-pipes for the LED indicators. The label was made using a laser printer label and transparent sticky plastic film. A pdf of this artwork is available on the Circuit Cellar code & files download webpage.
The board layout is critical. If you intend to do this yourself, you must keep the input attenuator symmetrical and observe the manufacturer’s layout guidelines for the ADA4817s, which will happily oscillate at 250 MHz given half a chance. Trust me, I learned this the hard way. Use short traces, use the special “feedback” output pin and do not use a ground plane in this area. You should also take care with the layout of the DC-DC converter, keeping loops small and the whole lot far from the sensitive analog circuitry. Figure 4 shows the completed circuit board in the case.
Assembly was straightforward, with the DC-DC converter chip being the only leadless part that takes a bit of care to solder by hand. I stuck with 0805 and larger components where possible, to make things a bit easier for myself.
TESTING AND CALIBRATION
Once you have built the differential probe, you need to go through a simple calibration and testing procedure.
1. Check that the ±5 V supplies are present and at the right value when the power switch is in the x10 or x100 position. The power LED should be lit. Make all the tests with the power on.
2. Temporarily short C13, to eliminate the effect of the offset adjustment on the input attenuator.
3. Adjust the CMRR. Connect a high but safe DC voltage between both inputs and ground. I used 60 V from my ±30 V bench supply. Connect a digital multimeter between TP1 and TP2. Adjust VR1 (CMRR) to null the voltage between these inputs as close to zero as possible. You should be able to get down below 60 µV (-120 dB) with a bit of care.
4. Adjust the DC offset. Connect the voltmeter between TP5 (the output) and ground. Remove the short from C13, connect the two inputs together and adjust VR2 (Offset) for the lowest possible output voltage. You will need to switch between ranges frequently to dial in the best compromise. It will be unlikely you can get to zero on both ranges, but you should be able to get below ±2 mV on each without too much trouble.
5. Adjust the frequency compensation. Feed a 1 kHz square wave into the positive input with respect to ground. Crank up the amplitude on your signal generator as far as it will go. Set the probe to the x10 setting. Connect your oscilloscope to the probe via a BNC-to-BNC cable. Ensure the scope is on the high-impedance setting and any bandwidth limiting is off. You should now be able to trigger on the square wave and adjust the compensation trimmer VC1 for optimum compensation, just as you would compensate a standard x10 probe. The correct compensation is achieved when the rising edge of the square wave shows no overshoot or undershoot. Use a non-metallic tool to make this adjustment. Repeat the process for the negative input and VC2.
I found designing and building this project very satisfying. The opportunity to design a project that does not include a microcontroller and required me to dust off my analog design skills was a welcome change. The end result is a useful instrument that exactly meets my needs and is in regular use on my bench.
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PUBLISHED IN CIRCUIT CELLAR MAGAZINE • APRIL 2019 #345 – Get a PDF of the issueSponsor this Article
Andrew Levido (firstname.lastname@example.org) earned a bachelor’s degree in Electrical Engineering in Sydney, Australia, in 1986. He worked for several years in R&D for power electronics and telecommunication companies before moving into management roles. Andrew has maintained a hands-on interest in electronics, particularly embedded systems, power electronics, and control theory in his free time. Over the years he has written a number of articles for various electronics publications and occasionally provides consulting services as time allows.