Gone are the days when all digital ICs ran off the same 5V power rail. As CMOS technology overshadowed 5V TTL, we moved into an age of multiple voltages—3.3V, 2.5V, 1.8V, 1.2V or even 0.8V. Chances are your next design will need to interconnect two chips using different supply voltages. In this article, Robert explains the problems you may encounter doing this voltage translation, and he describes some solutions.
Welcome to “The Darker Side.” Fifty years ago, nearly all digital circuits used TTL (transistor-transistor logic) chips from the ubiquitous 74xx or 74LSxx families—introduced in 1964 by Texas Instruments (TI). All were powered from a 5V rail, a voltage selected to provide enough headroom for good working of the bipolar transistors. Because all circuits were using the same silicon technology and voltage levels, any output could then simply be connected to any input without any concern. The life of a digital circuit designer was easy.
Some years later, in 1968, another technology named CMOS (complementary metal-oxide semiconductor) was invented by RCA. CMOS had a slow start, but had a wider adoption from the late 70s. These chips were initially slower than TTL, but provided considerably lower power consumption. The CMOS CD40xx and 74HCxx families are good examples of this first generation. These chips could operate over a wide voltage range, usually from 3V to 18V, so they could be powered under 5V as TTL chips. However, the behavior of CMOS transistors is not the same as the bipolar transistors used in TTL chips. As a result, some subtle difficulties appeared when interconnecting them with TTL chips, even if they used the same power voltage. Manufacturers then introduced variants of CMOS chips designed to be compatible with TTL, such as the well-known 74HCTxxx family.
The trend toward lower power consumption and higher speed was just starting, and in the following years we saw plenty of other variants, using improved CMOS technologies and lower power voltages: 3.3V, 2.5V, 1.8V, 1.2V or even 0.8V. Consequently, the list of digital chip families exploded: AHC, LV, ABT, AC, AHCT, ALVT, LVC, AUC, AUP, AVC and others. Similarly, microcontrollers (MCUs) are now available with plenty of I/O voltages and options.
Are you starting to get lost? Well, you’d better not, because in your designs you will likely need to interconnect two chips using different supply voltages or different CMOS logic technologies. In this article, I will discuss the problems you may encounter and some of the usual solutions. So, take a seat and enjoy.
WHAT’S THE PROBLEM?
I don’t plan to present a hundred different logic families, for two good reasons. First, it would be more than boring, and second, you can easily find good readings on that subject from online resources. Have a look, for example, on the TI website. The company’s Logic Guide is a good starting point .
Instead, let’s take a look, as an example, at the datasheet of a standard CMOS logic gate—the SN74AC00 NAND circuit from TI. More precisely, let’s look at its main voltage characteristics. These are extracted from the datasheet and shown in Table 1 and Table 2. If you are not familiar with this device, I encourage you to download its datasheet  and take a look for yourself. Table 1 shows the recommended operating conditions. As you can see, Table 1 shows that the chip could be powered from 2V to 6V.
Let’s assume for simplicity that the power source you want to use is 3V, which is well within these limits. With a 3V power supply, the datasheet states that the recommended minimum high-level input voltage, noted VIH, is 2.1V. On another line, the datasheet says that the input voltage VI must stay between 0V and VCC. Therefore, a “good” input voltage for logic 1 is between 2.1V and 3V. Similarly, the maximum low-level input voltage VIL is specified as 0.9V, so an input voltage between 0V and 0.9V means logic 0.
OK, but what happens with this chip if an intermediate voltage is applied to its input, between 0.9V and 2.1V? Will it be understood as a logic 0 or as a logic 1? The datasheet doesn’t say. Instead, it tells you to avoid such a situation! This means that the manufacturer doesn’t commit to a given behavior. It could give a 0 or a 1, but it could also give either a 0 or a 1 depending on the ambient temperature, on chip-to-chip variations or on anything else. It could also put the chip into a non-specified mode, such as producing oscillations on the output, or giving a non-specified voltage on the output. In a nutshell, you have to respect these recommended operating conditions. Period.
Now let’s have a look at the second part of the information from the SN74AC00 datasheet. Its so-called electrical characteristics are shown in Table 2. Here, you will find what the manufacturer specifies in terms of voltage on the outputs of the chip. VOH is the guaranteed minimum output voltage when the output is at a high logic level. Here it is specified as 2.46V with a 3V power supply and a 12mA load on the output. This means a logic 1 on the output is any voltage between 2.46V and VCC=3V. Similarly, VOL is the guaranteed maximum output voltage when the output is tied to a logic low, and it is 0.44V with the same 12mA load.
I have reproduced this data graphically in Figure 1. You can see that the guaranteed output voltages for any logic level are within the accepted input voltages for the same logic level. This is a must, in order to safely connect some outputs of the chip to its own inputs. Using the denomination that I introduced before, we have:
VOL < VIL and VIH < VOH.
These conditions are nearly always true if you use a single chip with a single power voltage, or even several chips using exactly the same technology. However, as you’ve probably guessed, the situation is more complex when several technologies are mixed on the same circuit, and they often have to be. Each chip has its own particular datasheet and specifications, and you will have to check them in detail. For the sake of simplicity, JEDEC (Joint Electron Device Engineering Council) has defined some standard values that are more or less observed by manufacturers. Figure 2 contains a compilation of all the main JEDEC standard 8-5 specifications, from 5V-TTL to 1.8V CMOS. I found this illustration in a tutorial published by Analog Devices, “Low Voltage Logic Interfacing” , which is worth reading.
From Figure 2, you can see that things always work fine when an output at a low logic level is connected to any input, at least with technologies from 5V down to 1.8V. For those variants, output voltages are always below 0.5V for a 0 (VOL ≤0.5V), and the maximum input voltage for a zero is always above this level, even for 1.8V logic (VIL =0.63V). So, we always have VOL < VIL—no problem here. Once again, this is true down to 1.8V but not below. With that in mind, you’d better take care when using very low voltage technologies, such as 1.2V.
The situation is much more complex, however, for high logic levels. Two problems may occur. An output voltage may be too low to be understood as a 1, or too high to avoid exceeding the rating of the receiver. Imagine, for example, that the output of a 3.3V CMOS circuit is connected to the input of a 5V CMOS circuit. For the former, a 1 means a voltage above 2.4V, but for the latter 2.4V lies in the undefined region (1.5 to 3.5V). It could work, but maybe only from time to time. Conversely, imagine that the output of a 3.3V CMOS device is connected to the input of a 1.8V circuit. The output voltage for a logic 1 will be between 2.4V and 3.3V—in any case far above the power supply of 1.8V of the receiver. If this receiving device tolerates above-the-rail voltages, that will be fine. If not, you may end up with smoke and tears.
Don’t get me wrong here. I am not telling you that directly interconnecting two chips from different logic families or with different supply voltage never works. But you must absolutely check their specifications in detail. Have a look at their respective VOL, VIL, VIH and VOH, and decide for yourself if some level adaptation circuits must be added or not.
Now, how to do it? First, if you are free to select any logic family, then you will probably find a working configuration even if the supply voltages are not the same. Look again at Figure 2. If you double check, you will see that at least the families 5V TTL, 3.3 LVTTL and 2.5V CMOS show a form of compatibility. The VOH of any of them (2.0V or 2.4V) is above the VIH of all of them (1.7V or 2.0V). This means that among these three families, a 0 or a 1 will always be received correctly. In that case, the only remaining risk is to exceed the maximum input voltage rating, if a high-voltage part is connected to a lower-voltage one. For that purpose, some chips are designed to support over-voltage signals on their inputs—but not all of them do, so you’d better double check carefully.
If you need to reduce the output voltage to comply with the maximum rating of another chip, then a simple attenuation network may be enough. Let’s look at an example. Imagine that you need to connect the output of a 3V3 LVTTL chip to the input of a 1.8V CMOS device that isn’t over-voltage tolerant (Figure 3). The output of the first chip for a logic 1 could be anywhere between VOH = 2.4V and VOH = 3.3V, and must be converted to a voltage between VIH = 1.17V and VMAX = 1.8V+0.3V=2.2V. Here two discrete solutions could be used. First, you could build a voltage divider with two resistors. Look again at Figure 3. An easy calculation shows that using a 1.5kΩ and a 1.6kΩ resistor in series does the trick. Take care to verify that the reduced voltage satisfies the two conditions: It must always be above the minimum input voltage of the receiver for a logic 1, and must never exceed its maximum rating.
The second solution is to build a voltage clamping circuit using a resistor and a low-dropout diode, typically a Schottky diode connected to the 1.8V power supply as illustrated. This diode doesn’t conduct when the voltage is below the 1.8V rail, but otherwise limits it to some hundreds of millivolts above this limit. Both solutions will work, at least as long as the digital signals are slow enough. When the signals get faster, the parasitic capacitance of the resistors and wires must be taken into account. To load these parasitic capacitors quickly, you will need to use low-value resistors, which then will increase the power consumption and load on the logic output.
OK, so going from a high-voltage device to a lower-voltage one is easy, at least for signals that are not too fast. But what about the other way around? Imagine that a 1.8V CMOS output must be connected to a 3.3V LVTTL input. What could you do? Connecting them directly will not work reliably, since the minimum output voltage of the 1.8V device for a logic 1 is quite low (VOH =1.35V). This is lower than the minimum required voltage for the 3.3V LVTTL input (VIH = 2.0V). As shown in Figure 4, you can find a way to amplify this voltage using transistors, here a pair of NPN bipolar transistors powered from the higher-voltage rail. But far simpler solutions do exist, as illustrated on the lower part of Figure 4. In that case, you would simply use a dedicated voltage translator IC.
Literally thousands of variants exist, so you will surely find an appropriate circuit for any application. The difficulty, if any, is to select the proper one. Fortunately, chip manufacturers provide nice, web-based tools to help the process. One of these tools is the Unidirectional Voltage Translation tool provided by TI (Figure 5) . Just enter the input and output voltage ranges, the number of signals you need to translate and click on a button to get some recommendations. Of course, the tool only recommends chips from a single vendor, so you’ll need to try some of them and compare the results. For my example, the tool suggested a SN74LV1T34 circuit , which does the trick and is recommended in very small packages (SC-70 or SOT-23). Moreover, you will be able to buy dozens of them for the cost of a coffee ($0.07 unit cost per 1,000). In a nutshell, using a specific voltage translation chip often makes sense.
Up until now, I’ve talked about simple, unidirectional logic signals. But bidirectional signals also may need voltage translation. What are the possible solutions? Basically, they can be split in two classes: Direction-controlled voltage translators and auto-bi-directional voltage translators.
Let start with direction-controlled voltage translators. As the name says, these circuits can be used when you have a set of bidirectional signals to translate between two voltage ranges, but also a signal indicating in which direction the information flows. The typical example is between a microprocessor and a peripheral chip such as a memory or I/O chip, connected by address and data parallel buses. Both may be using different voltage levels, and the data bus may be bidirectional, but there is always an R/W (read/write) signal coming from the microprocessor and indicating if the operation is a read or a write. In that case, you will just need to find the proper direction-controlled voltage translator and wire it correctly, using the R/W signal as a direction indicator.
Of course, using the same voltage everywhere is simpler. But, once again, this is not always possible. For example, you may be working on a recent microprocessor-based system, using only 3.3V CPU and memory chips, but need to interconnect a vintage 5V-only parallel-bus chip—a legacy CAN controller for example. (Or, maybe your customer has thousands of these chips in its warehouse and wants to use them?) In that case, you will add voltage translating circuits on all lines between the 3.3V domain and the 5V domain, as illustrated in Figure 6. In such an application, a simple 3.3V direction-controlled bus transceiver could be used, as long as its inputs are 5V-tolerant. A good match here could be the 74LVC245 (Figure 7), available from several suppliers including Nexperia  (formerly NXP Standard Products division).
Last but not least, there are situations in which you may need to do a voltage translation on a bidirectional signal, but without any way to easily know in which direction the signal goes. An I2C bus is a good example. This type of bus interconnects plenty of chips using two lines, clock and data. The data signal may be driven by any circuit on the bus, and even the I2C clock signal may be bidirectional in multi-master systems. And, yes, some I2C chips use different voltages, so voltage translation may be needed. The difficulty here is that there is nothing like a direction signal that you can use to drive the voltage translator, except with a complex decoding of the I2C protocol itself. In this situation, you will need a voltage translator from the second family—a so-called auto-bidirectional voltage translator. These don’t need any direction signal.
How can this be possible? Well, these devices are usually based on a strangely simple circuit. The basic setup uses only one FET transistor and two resistors. I ran a SPICE circuit simulation of a simple 3.3V-to-5V auto-bi-directional translator. The schematic and simulation results are shown in Figure 8. On the top, a 3.3V logic signal is applied on the left-side port. It exits on the right-side port with a 5V amplitude. On the bottom, a 5V logic signal is now applied on the right-side port, and is reduced to 3.3V on the left-side port. How does it work? In fact, it is quite simple. When either side is pulled low, the FET transistor is activated and pulls the other side low. When neither side is pulled low, the transistor stays open and the voltages on each side are driven up by the two pull-up resistors, each connected to a given power supply. Therefore, there is no need for a direction-control signal. This circuit automatically adjusts the voltage on either side.
Any downsides? The first is that zero levels are not converted. If one side pulls down the line to 0.8V, the other side will be at 0.8V, too, not lower. With that in mind, this circuit may not be adequate when using very low voltage logic levels. The other downside is that the speed of this circuit is quite low, especially for the low-to-high transitions. This is clearly visible in the simulation in Figure 8, which was done with 1MHz signals. The root cause of this slow response is that the pull-up resistor must load all parasitic capacitors of the FET transistor, and this takes some time.
Speed is improved with lower values for the resistors, but this increases the power consumption and the load on the logic outputs. Fortunately, chip manufacturers have improved this basic circuit, adding speed-up circuitry. In rough terms, they detect the low-to-high transitions on the inputs, and switch on temporarily an accelerator circuit to strengthen the output signal transition. An example of such a circuit is the MAX3370 from Maxim Integrated, illustrated in Figure 9 . Faster but similar solutions are available from Analog Devices, such as the ADG3301 , which supports signals up to 50Mbps, still without any need to select the direction.
If you’ve never worked on a multi-voltage logic circuit, maybe you are surprised by this apparent complexity. Why can’t we just use 5V only? Or maybe 3.3V only? Well, the trend toward low power and fast circuits won’t be stopping anytime soon. And physics tells us that a reduction of the power supply voltage always reduces the power consumption of a device for the same speed. Therefore, new high-performance chips will continue to use lower and lower voltages, as technology permits. So, a designer who wants to use the best solutions will have to use one of these cool ultra-low voltage chips, but probably alongside some older chips for other functions on the board. And the use of voltage translation techniques likely will then be mandatory.
Anyway, I hope you see that there are plenty of easy-to-use chips to help you in these voltage translations. As always, the most important thing is to answer some key questions when you design your schematic. Are several voltages present? Are all signals compatible with each other in terms of voltage? Is there a risk to have either an undefined logic level or to exceed maximum ratings? If so, open your bag of tricks and select the proper solution.
 Logic Guide
 SN74AC00 quadruple 2-input positive-NAND gate
 MT-098 Tutorial: Low Voltage Logic Interfacing
Analog Devices Inc
 Voltage level translators search engine
 SN74LV1T34 Single Power Supply BUFFER Logic Level Shifter
 74LVC245A Octal bus transceiver; 3-state
 MAX3370 – 1µA, 2Mbps, Low-Voltage Level Translators in SC70 and µDFN
 ADG3301 – Low Voltage 1.15 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator
7400-series integrated circuits
4000-series integrated circuits
Voltage Translation Buying Guide
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • DECEMBER 2020 #365 – Get a PDF of the issueSponsor this Article
Robert Lacoste lives in France, between Paris and Versailles. He has more than 30 years of experience in RF systems, analog designs and high-speed electronics. Robert has won prizes in more than 15 international design contests. In 2003 he started a consulting company, ALCIOM, to share his passion for innovative mixed-signal designs. Robert is now an R&D consultant, mentor and trainer. Robert’s bimonthly Darker Side column has been published in Circuit Cellar since 2007. You can reach him at firstname.lastname@example.org.