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Understanding the Ultra96 Board (Part 1)

Written by Nishant Mittal

The Hardware

Prototyping boards are an important tool for the creative system design process. Nishant is a particular fan of the Ultra96-V2, an Arm-based, Xilinx Zynq UltraScale and MPSoC development board based on the 96Boards open specification. In this two-part article series, Nishant takes a deep dive into the Ultra96 board and how to get started using it for development. Part 1 explores the hardware aspects of the board.

  • How to understand the hardware features of the Ultra96-V2 board
  • The overall design and form factor
  • How does the voltage regulation work n the Ultra96?
  • The Wi-Fi module on the Ultra96
  • Ultra96-V2 board from Avnet
  • PYNQ software from Xilinx
  • ZynqMP FPGA: Xilinx part number: XCZU3EG-1SBVA484I
  • PetaLinux 
  • PMIC regulators IRPS5401MTRPBF and IR38060MTRPBF from Infineon
  • Fixed-voltage regulators from ON Semiconductor: NCP177AMX180TCG, NCP134AMX090TCG and NCP716MT33TBG.
  • Programmable clock generator from Renesas Electronics: 5P49V6975A114LTGI.
  • LPDDR4 DRAM from Micron Technology

Prototyping boards and evaluation boards are a critical part of any embedded system design. These boards are like scribble paper for a system designer, enabling them to put a design idea into action before proposing it to customers, or to develop custom hardware for deployment customers. For my part, I’ve been using a variety of prototyping boards in the past. In my Circuit Cellar articles, I’ve discussed Cypress PSoC boards, Arduino boards and Raspberry boards. For quite some time, I’ve been using the Ultra96 board from Avnet that sports a Xilinx FPGA.

In this two-part article series, I’ll do a deep dive into this board, and hopefully this will help you get started without doing much research on it. The deeper motive of this article is to make people aware of various circuit and board details that are necessary for crafting an error free design. In this first part of this article series, I’ll explore the hardware aspects of the board, and then get to the software side in Part 2. All the information gathered for this article comes from 96boards.org and from my own experiments.

DIAGRAM AND FORM FACTOR

Figure 1 shows the block diagram of the Ultra96 board [1]. The Ultra96 board was primarily designed as an inexpensive, reliable experimental FPGA system, built to provide the best user experience for both hobbyists and professional system designers. Ultra96 provides the functionality to allow users to experiment on their design wirelessly. That said, some hardware designs may require a wired connection for programming the programmable logic. The bootable Linux provided on the board, using state-of-the-art PetaLinux and PYNQ software, enables you to bring your design idea into reality. PYNQ is an open-source project from Xilinx that uses the Python language and libraries.

FIGURE 1 – Block diagram of the Ultra96 board

The Ultra96 board incorporates a ZynqMP FPGA (Xilinx part number: XCZU3EG-1SBVA484I). The FPGA in itself is a complete system-on-chip (SoC) that embeds an Arm Cortex A53 (APU) and dual core Arm Cortex R5 (RPU) along with programmable logic on chip. This huge FPGA allows for a very clean and complete system, with no extra processor required on board. From a programmable logic point of view, the FGPA includes configurable logic blocks (CLBs), 36KB Block RAM (BRAM), Unified RAM (URAM), DSP blocks and JTAG block chains. Together, these provide a huge space, not only for embedded systems, but also data centers and many other applications.

The Ultra96 provides several connectors that support both high speed and low speed interconnects. Among the interface support provided are display interfaces, camera links, I2C, SPI, UART and GPIOs. There is also microSD, Wi-Fi, USB 3.0 and JTAG—all of which enable users to interact with the board, and put their ideas into action. There is 2GB of built-in LPDDR4 DRAM, a huge amount memory that’s sufficient for any intermediate embedded application.

Figure 2 shows the form factor of the board. On the top side of the board is the I/O header, UART debug header and USB connector. The board’s Wi-Fi module is placed on top of the board, while the ZynqMP FPGA and LPDDR4 are placed on the bottom of the board. There is a camera connector available which can be used for camera or display interfacing, or even as a GPIO port. Note that camera can be connected to the board in many ways. You can use a compatible connector; you can use a daughter card connected to the ports, which can have the camera interconnection; or you can use USB as the camera interconnect.

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FIGURE 2 – This shows the form factor of the Ultra96 boards—top view (left); side view (right).

A built-in Display Port (DP) interface can be used to connect the Ultra96 to the display. And you can use UI-based Linux operating systems (such as PYNQ or PetaLinux) for creating applications as well as demonstrating the outputs. There is a JTAG connector through which you can do JTAG debug or perform direct JTAG programming of the hardware. On the bottom side of the Ultra96 board, there is a small fan that provides air flow for Zynq-MP. That’s helpful, because the Zynq-MP does a huge amount of processing with Linux running on top of it. That’s key for embedded use cases that require the board to run for more than 24 hours.

VOLTAGE REGULATION

There are many voltage regulators on the Ultra96 board. These deliver reliable DC voltages to different parts of the board. Thanks to today’s modern programmable regulator technology, systems can operate within stable temperature ranges, even at high power. This makes life easier for system designers. Let’s consider an example scenario where multiple voltages are managed from a single regulator. In the past, such designs required multiple LC circuits with switches to toggle between voltages. The huge added capacitance meant power spikes, and designing PCBs to accommodate such circuitry became a headache. Now, with PMBus technology, which is a successor of I2C, this bottleneck has been solved. With just I2C programming, you can support a huge range of voltages with just small amounts of circuitry.

With all that in mind, let me provide a short briefing on PMBus. PMBus is the derivative of I2C protocol, which allows power management via I2C bus. A PMBus can be used to control, configure as well as monitor PMBus devices via I2C BUS. In other words, in PMBus, the power management sequence is sent on top of I2C bus.

Figure 3 shows the data sequence required for PMBus write operation. As seen in Figure 3, first a start signal is sent. Next the slave address is sent with a R/W (read/write) bit, where 0 signifies write. Once the acknowledge bit is high, command codes are sent. Command codes provide various features for a power rail. These can include overvoltage max., min. limit, undervoltage limits, fault limits, required voltage, current min. and max. settings and so on. The read sequence is the same as write sequence, however it requires a repeated start in between the command code and slave address. Figure 4 shows the read sequence of the PMBus.

FIGURE 3 – Write sequence (Image courtesy of PMBus.org [2])
FIGURE 4 – Read sequence (Image courtesy of PMBus.org [2])

Let us first look at the schematic of the Ultra96 board. A link to the full schematic is available in RESOURCES at the end of the article [3]. We see that there are two main PMIC regulators: the IRPS5401MTRPBF and IR38060MTRPBF from Infineon Technologies and three small fixed-voltage regulators from ON Semiconductor which are NCP177AMX180TCG, NCP134AMX090TCG and NCP716MT33TBG.

Now let’s dive into details of one of the regulators, the IR38060MTRPBF (IR38060). Note, all of the regulators are PMBus compatible and follow the same design scheme. The IR38060 is a synchronous buck converter with a PMBus interface in a PQFN package. The IR38060 has PMBus configurability to control output voltage, soft-start, input undervoltage-lockout (UVLO), input overvoltage protection, output overvoltage protection, output overcurrent protection, “Power Good,” thermal protection and switching frequency.

A single VIN along with an internal LDO (low-dropout regulator) generates VCC from PVIN. Another internal LDO generates the 1.8V needed by the internal digital circuits. Figure 5 shows the input and output of the regulator. Note that it is always recommended to have a diode for an input coming from an external source. The reason is that we can’t know what could come from the external world. The diode will not only prevent reverse voltages, but will also keep out any badly filtered DC signal. If you look at the regulator circuits in general, there are lot of decoupling capacitors placed on the single rail. The reason for this is that the total impedance for the entire frequency range gets covered, which then effectively reduces any rail noise.

FIGURE 5 – Shown here are some important parts of the regulator circuitry on the Ultra96 board (Source: www.96boards.org).(Click to enlarge)

On the PCB layout side, it is always recommended that the switching path of the LC be as short as possible. Having a long switching path adds the ripple and can cause unnecessary spikes and bad DC signals. A proper ground filling is necessary to have a good return path throughout.

THE Wi-Fi MODULE

Now let’s examine the radio (Wi-Fi) part of the board. Placing an antenna on board can be a big headache for designers—and this board is no different. If you observe the board’s layout, you can see that the PCB designer had to compromise the placement of the FPGA versus that of the Wi-Fi module. Wi-Fi modules have stringent requirements as to their placement, their height from the casing and proximity to surrounding PCB traces. All these contribute to lower signal and performance. One of the major design specifications for the Wi-Fi module is that the ground should not be surrounded around the device. Ground planes are signal absorbers. If you look at the Ultra96 PCB carefully, you’ll see that the antenna side of the module is placed away from the ground plane and there is no ground plane pouring around the antenna module. Figure 6 shows a section of the board design displaying the Wi-Fi module placement.

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FIGURE 6 – Wi-Fi module placement (Source: www.96boards.org)

The schematics of the Ultra96 show that there are lot of ESD diodes on board. These ensure that a sudden spike of current will be absorbed and damage the diode instead of the costly ICs on the board. The board is well encased and includes a mounted fan to cool down the FPGA, which can heat up due to excessive amounts of processing.

The devices on board are clocked using sources either from the built-in PLL (phase locked loop) within the ZynqMP FPGA, or using the programmable clock generator from Renesas Electronics (formerly IDT), the 5P49V6975A114LTGI. This clock generator is an I2C programmable device with four output pairs compatible to LVCMOS, LVPECL, LVDS or HCSL. Because the device has an internal crystal oscillator, we don’t need to have an external crystal oscillator added on the board. The device is flexible for voltage sources of 1.8V, 2.5V or 3.3V. On this board, by default, the clock of the PS (processing system) is 33.33MHz, the USB clock is 24MHz and the Display Port clocks at 27MHz (LVDS).

VARIETY OF INTERFACES

The Ultra96 provides a rich set of interfaces for SD-, USB-, I2C-, SPI- and UART-based devices. These devices can be connected to the FPGA using the MIO/EMIO (Multiplexed I/O / Extended Multiplexed I/O) pins of the FPGA. Again, the entire schematic can be found on the 96boards website [3]. For memory, the board provides an LPDDR4 DRAM from Micron Technology, the MT53D512M32D2DS-053 AIT:D. This is a 16GB SDRAM organized as 512MB×32 and clocked at a maximum frequency of 1,866MHz. The maximum supply voltage of the device is 1.1V with operating temperature ranging from -40°C to +95°C. This SDRAM is available in a WFBGA package. For such high-speed devices in general, it is recommended to have the decoupling capacitors as closed to the pin as possible. The PCB traces should be designed with 40Ω interface impedance.

In this part of the article series, we are not discussing the various MIOs and EMIOs available on the board. We will get more insights about MIOs when we discuss the Vivado designs for this board.

CONCLUSION

In this article, we took a deep dive into the various aspects of Ultra96 board, which is based on the ZynqMP FPGA from Xilinx. We explored the component placement, hardware design and board details. We also went through some of the important components on board. In Part 2, we will look at how to put the Linux OS into action on the Ultra96 board. 

RESOURCES

References:
[1] Product page: https://www.96boards.org/product/ultra96
[2] http://pmbus.org/Assets/Present/Using_The_PMBus_20051012.pdf
[3] Schematic: https://www.96boards.org/documentation/consumer/ultra96/ultra96-v2/hardware-docs/files/ultra96-v2-schematics.PDF

Xilinx reference: https://www.mouser.in/datasheet/2/903/ds891-zynq-ultrascale-plus-overview-1662253.pdf

96Boards.org | www.96boards.org
Avent | www. www.avnet.com
Infineon Technologies | wwwi.nfineon.com
Micron Technology | www.micron.com
ON Semiconductor | www.onsemi.com
PYNQ | www.pynq.io
Renesas Electronics | www.renesas.com
Xilinx | www.xilinx.com

PUBLISHED IN CIRCUIT CELLAR MAGAZINE • DECEMBER 2020 #365 – Get a PDF of the issue


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Nishant Mittal is a Hardware Systems Engineer in Hyderabad, India.

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Understanding the Ultra96 Board (Part 1)

by Nishant Mittal time to read: 9 min