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Optimizing Clock Resources in FPGAs

Written by Colin O'Flynn
This article is a case study of why you should pay attention to the underlying architecture your HDL code is running on. The use of the simple clock buffer is explored in the Spartan 6 FPGA, and a demonstration of where you might run into placement errors and how you can fix them is given. More generally, this explores the use of the FPGA Editor to get a feel for how your design is being implemented on the physical hardware. Topics Discussed How to optimized resources in FPGAsHow to find FPGA placement errors and fix themHow to use an FPGA editor Tech Used Spartan 6 FPGA from Xilinx Many FPGA projects live mostly in the HDL design world, being composed of blocks built entirely in Verilog or VHDL. A handful of special FPGA resources might be pulled in, such as clock generators or buffers. But as your project gets more complex, ignoring the underlying architecture of the FPGA that your design is running on gets more and more dangerous. It might mean you have trouble completing a place and route run, or that the design is marginal under certain conditions. This column will discuss some issues around clock placement and routing. While there is much to be written about the subject, I wanted to give you a quick introduction and demonstrate that it’s actually pretty easy to get your hands dirty doing a little manual placement or optimization. And it might give you a lot more breathing room when it comes time to expand your design! One thing I won’t be discussing in this column is ensuring your clock has proper constraints, such as telling the tools what sort of frequency input the clock has and the relationship between data input/output and the clock. Proper constraints are critical for a working design, so it’s something I’ll tackle in a future column. In the meantime, you can refer to Austin Lesea’s five-part set of posts, “Timing Constraints,” for a quick introduction (see Resources). PLACEMENT PROBLEMS I’m going to be usin
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Optimizing Clock Resources in FPGAs

by Colin O'Flynn time to read: 12 min