IC Design Essentials (Part 3)

8-Bit Timer Design with 180-nm CMOS Technology

Last time, Nishant covered design modeling and layout techniques. In this article he details the final stages of the design process using 180-nm CMOS technology.

How to do 8-bit timer design with 180-nm CMOS technology

TSMC’s 180-nm model file
Magic VLSI Layout Tool 8.0
from Open Circuit Design
ngspice Circuit simulator

Timers and counters are very important blocks in a microcontroller. Microcontrollers have built-in timers and counters that manage various delays, frequencies, and real-time applications. In this article, I’ll focus on the process of designing on-chip 8 bit timers for microcontrollers. These can be further replicated to Timer1, Timer2, Timer3, and so on as per your requirements with minor modifications.

For this design, I implemented Taiwan Semiconductor Manufacturing Company’s (TSMC) 180-nm model file, which is free when used for learning purposes. I used ngspice-based simulation software for this project. Once the design was validated, I worked on the design with the Magic VLSI layout tool, which is CAD software for laying out a MOSFET-based chip. I used Windows 7, but you can use Windows 8 or even an Ubuntu-based operating system. ngspice and MAGIC are open-source tools for CAD designs that you can download for both Windows and Linux.

SYSTEM IMPLEMENTATION

Figure 1 is a basic diagram showing the microcontroller’s timer block. Figure 2 shows a 1-bit timer’s circuitry. The multiplexer has two select lines (S0 and S1) and inputs (M and x – 1). M is the input data given by user. When S0 and S1 is set to 0 0, it loads the data into the system by taking the M value. When S0 and S1 become 0 1, decrementing starts. The Register stores the value until the strobe signal passes the value and takes a new value. The column is repeated eight times to complete 8 bits. The initial borrow is taken as high to start the counting.

Figure 1
Figure 2

Figure 1 Timer block diagram — Figure 1
Timer block diagram

Figure 2 The circuit design for a timer chip — Figure 2
The circuit design for a timer chip

Once the output completes the entire 8 bits, it generates a 1 out of comparator. This is the timer output, which waits until the count is completed. Once the count is completed, it sets the output high. This timer can be configured into a higher bit (i.e., 16 bits) simply by replicating the 8 bits again. Here, the decrementer is the subtractor, which generates the subtract and borrow output. The timer is such that after counting of all the 8 bit pulses the output lines of all the decrementer would be 0 and by using NOR operation, we get a logic high after the count is completed. Figure 1 shows the block representation of the same. By repeating this as a block eight times, you can design an 8-bit timer.

The D flip-flop is designed as positive edge-triggered flip-flop with minimum sizing. This is a single-stage positive level triggered flip-flop. You can make this negative by alternating the clocks’ positions. By cascading a negative level and positive level in a master-slave arrangement, a positive edge-triggered flip-flop is constructed.

Figure 3 shows the layout and waveforms. A 2:1 multiplexer was designed with the waveform and layout in Figure 4. When S1 is selected, x – 1 is copied to the output D. When S0 is selected, M is copied to output. A register is nothing but a flip-flop with facility of Enable. When Enable is active high and fed with 1, then the register takes the input fed by the user. When it is logic low, the register latches the previous output until Enable becomes 1. Here, “d1” is input, “out” is output, “En” is enable, and “a” is the clock. The enable displayed is active-low Enable; thus, when Enable is 0, it reads input while it latches when enable is 1. When EN is 1, it latches until En becomes 0. Once En becomes 0, it starts copying the input with delay. A decrementer is a circuit that decrements or subtracts the two inputs and gives the subtracted result along with the borrow if any.

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As I noted above, the 8-bit timer is designed using a cascade of eight 1-bit timers. First of all, a 1-bit timer was designed and tested. Thus, it was continued to 2 bits and finally 8 bits. The layout and the waveform for the decrementer are shown in Figure 5. The waveform for the register is shown in Figure 6.

Figure 3
Figure 4
Figure 5
Figure 6

Figure 3 D flip-flop layout and waveforms — Figure 3
D flip-flop layout and waveforms

Figure 4 Multiplexer layout and waveformsa — Figure 4
Multiplexer layout and waveformsa

Figure 5 The decrementer — Figure 5
The decrementer

Figure 6 Waveform for a register with active-low Enable — Figure 6
Waveform for a register with active-low Enable

Once all the blocks are made and tested, I integrated them into a single bit timer. The process of moving forward with this massive chip is as follows: make individual elements as a subcell; design a 1-bit timer integrating all the elements; design a 2-bit timer by using the 1-bit timer as a cell repeating it two times; perform post layout simulation; now using this 2-bit timer as a subcell and make 4-bit timer and test its post-layout simulation; and, finally, use the 4-bit timer as a subcell, make an 8-bit timer, and test the post-layout simulation.

Following these steps, it’s very easy to debug the interconnection mistakes. Since this is a digital chip, it isn’t too difficult in terms of laying out the floor plan. However, you must take of clocking. Apart from that, having more contacts also helps reduce the resistances.

There are situations in which the clocking cannot be equalized using an H type of orientation. However, by adding inverters to the path, you can delay the nearby circuit’s clocks so that clocking happens in all the flip-flops at the same time. The chip also need pads. But for simulation and testing, the pads aren’t required.

Figure 7 shows the complete layout and waveform from the post-layout simulation. The pre-layout modeling of the design, post-layout program, and block-by-block programs are all posted on the Circuit Cellar FTP site. Refer to the txt file for a list of the files and their descriptions.

Figure 7 The 8-bit timer layout and waveform — Figure 7
The 8-bit timer layout and waveform

SIGNAL INTEGRITY CALCULATIONS

Consider the following signal integrity calculations:

Setup time = 75 ps
Hold time = 70 ps
S + H = 145 ps
D to Q delay = 454 ps
Φ to Q delay = 88.7 ps
t_{D_MAX} ≥ T/(2 – S_master)
t_{D_MAX} ≥ 2.105 × 10^–9
t_{D_MAX} ≥ –T/2 + HMASTER
t_{D_MAX} ≥ 805 ps

Since the first case in the following equation is satisfied, it’s predicted that the S-H delay of the first level trigger latch will come out to be almost the same as the positive edge-trigger flip-flop. We know the following:

Using an eight-input NOR requires more logical effort compared to a two-input NOR, so we use four two-input NOR gates to compare the counter results.

RESULTS

I designed an 8-bit timer and implemented it on a chip level. In this article series, covered the process from the initial design phase to post-layout simulations.

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SOURCES
Magic VLSI Layout Tool 8.0
Open Circuit Design | www.opencircuitdesign.com
ngspice Circuit simulator
Paolo Nenzi | http://ngspice.sourceforge.net/

PUBLISHED IN CIRCUIT CELLAR MAGAZINE • OCTOBER 2016 #315 – Get a PDF of the issue

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