This article is a prequel to Colin’s December 2015 article, “Building an FPGA Board.” Rather than showing you how to assemble a complex FPGA board, he provides some details and hints about how to design such a board. He covers how to design a complex board using the latest BGA-based FPGA parts while keeping costs under control.
Back in my article “Building an FPGA Board” (Circuit Cellar 305, 2015), I discussed how I solder BGA devices (such as FPGAs) using a low-cost reflow oven. In this article I will discuss the design of the FPGA board itself, which you could then assemble using the tips in my previous article.
I’ll assume you have a rough idea of which external parts you need, as they will be highly dependent on what you are trying to accomplish with your design. In addition to design-specific information, there are a few standards external requirements such as programming interface, communications, and power. This article will briefly cover some of these external requirements, but I’ll concentrate on how to physically lay out the FPGA board at a reasonable cost. Some of the topics I covered previously. For example, in “USB-to-FPGA Communications” (Circuit Cellar 299, 2015), I discussed the use of a generic USB microcontroller as a FPGA interface chip, which is very useful if you need to shuffle data to and from the FPGA.
So let’s assume you have a (mostly) complete schematic, and are wondering how to make this a reality. Let’s start with setting a target goal in terms of board requirements.
PCB SPECIFICATIONS
Assuming this design will be either a prototype run or possibly a small production run, it makes sense to design your PCB with specific requirements in mind to keep costs reasonable. The two PCB specifications you are most commonly told are the minimum “trace/space” (i.e., the minimum width of a trace and minimum spacing between copper features) and the minimum drill size.
As I mentioned in my previous article, I’m often using an overseas PCB fab (3pcb.com), although many other options are worth trying. They offer a variety of trace/space and drill size options, so I’ll target a 5-mil space/trace with 0.2-mm drill. This is a fairly “standard” technology option, so it shouldn’t be a problem when moving towards a small production run (i.e., a quantity of 100 to 200 units).
To give you an idea of what we’re working with, Photo 1 shows an example of the final PCB I designed and assembled. This uses a Xilinx Spartan-6 LX45 FPGA with an Atmel SAM3U microcontroller for high-speed USB communications.
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This six-layer PCB features a Spartan 6 LX45 FPGA, an Atmel SAM3U microcontroller, and a 10-bit ADC. I’ll overview some of my experiences designing this board in this column.
LAYER CAKE
In this example, I’m targeting a six-layer PCB. While you can get away with a four-layer PCB in some circumstances, it often results in trade-offs that I’d rather avoid. If you are targeting a more advanced design with DDR memory, I’d consider a six-layer board the absolute minimum, with an eight-layer PCB being a fairly likely option.
The stack-up of layers I’m using is given in Figure 1. This stack-up was the default for a local Ontario, Canada-based fab house (Lazer-Tech Ltd.) that I’d be using when moving towards a production run. While I didn’t validate if the overseas fab actually respected this stack-up, there were no controlled impedances required, so it was unlikely to affect my “alpha” prototype. I built a second validation unit based on the boards from the production run to confirm the actual stack-up had the required performance.
The standard stack-up used by my PCB fab, which I decided to keep for this project. An ideal stack-up might try to reduce the size of the 0.0140” core layer and increase the spacing between layer 3 and 4, which would improve the coupling to the GND and VCC planes of layers 3 and 4, respectively.
A common problem in high-speed signals (the red traces) is that the return current (shown in yellow here) is forced to go around a split in the reference plane. If this is impossible to avoid, capacitors can be used to bridge the gap, which allows the high-frequency return currents to take a shorter path than going around the entire split.
Using six layers allows me to have a solid unbroken ground plane, and a mostly unbroken power plane. The FPGA requires multiple voltages, so I’ve chosen to use a split power plane which is mostly a 3.3-V plane, with a small island of 1.2 V for the internal VCC voltage required by the FPGA. This power plane split requires very careful consideration to avoid routing signals across it.
Every signal needs somewhere for the return current to flow. Assuming this is a high-speed signal (e.g., clock, databus, etc.), we want the return current to flow as close underneath the signal as possible. Note that this return current is a high-frequency signal. This high-frequency signal may not flow on the ground plane, but instead flows on some other unbroken copper plane underneath the signal (such as the VCC plane). The path of the return current can be coupled to the ground plane by a capacitor between the VCC and ground plane.
Layers 1 and 3 can use Layer 2 (the ground plane) as the reference, whereas Layers 4 and 6 can use Layer 5 (the VCC plane) as a reference. This means every signal layer has a plane layer next to it. The split in Layer 5 means that if you route a signal across the power plane split, the return current has to flow around this split, as in Figure 2. If you want to see a real-life example of what happens, refer to my blog post on the topic (ProgrammableLogicInPractice.com).
For high-speed signals, it’s important to avoiding switching the reference plane too. For example, if I were to route a signal on the top layer (Layer 1) and then use a via to go to the bottom layer (Layer 6), this would mean the reference current would be transitioning from Layer 2 to 5 as well. While in an ideal world, high-speed signals wouldn’t change layers at all, if you do change layers, it’s best to keep the same reference layer. For example, go from Layer 1 to 3, so the return current is always flowing on Layer 2.
Decoupling capacitors connect the GND and VCC plane throughout the PCB (i.e., not only at ICs, but sprinkled throughout too). This provides a path for high-frequency return currents to switch between reference layers if needed.
You might notice from the stack-up that Layers 3 and 4 are closer together than they are to their respective reference planes. This was a downside of using the default stack-up, as ideally I’d increase the space between Layers 3 and 4 and have a reduced space between Layers 3 to 2 and 4 to 5. One could also match the spacing between the layers and their reference planes, which would be helpful if you needed controlled impedances. (I didn’t for this design.)
There are a number of other issues regarding signal integrity (SI) to be aware of; I can’t hope to cover them here, but I can point you in the right direction. If you’re looking for an online course to guide you through this area, I recommend two. Andy Eadie’s “EMC Pre-Compliance” course at EMCFastPass.com covers a number of issues related to both signal integrity and electromagnetic compliance. Eric Bogatin runs SI Academy (Bethesignal.com), which dives into more advanced SI topics. A great recent example of a specific SI issue is in Robert Lacoste’s article, “Digital Line Terminations” (Circuit Cellar 309), as he has some demonstrations on real test boards.
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As I mentioned, one critical aspect of high-speed signals is to avoid routing the signal across a break in the plane. This might happen because you’ve cheated and done a bit of signal routing on a power layer (very likely in a more constrained four-layer PCB), or you have split planes. Due to the nature of FPGA projects, it may be required that a signal gets routed across a split plane—for example, because the VCC-IO for an always-on microcontroller isn’t connected to the VCC-IO for the FPGA, which is switched on and off.
This means the signal will be required to transition between two different reference planes. In this case, it’s best to connect the split planes with decoupling capacitors, as in Figure 3. While not ideal, it provides a path for any return current flowing in the split plane to cross between. In Figure 3 the top-layer traces in red actually have an unbroken ground plane as a reference (not visible in the figure), so I’ve still tried to minimize the signals flowing over a split plane. Only the bottom-layer traces should use the split VCC layer as a reference plane.
An example of an impossible-to-avoid split situation: the two purple power planes represent an always-on VCC for the microcontroller, and a switched VCC for the FPGA. The capacitor circled in white is one of many that bridge the two planes, allowing high-frequency current to flow between them. The cyan traces are using this split plane as the reference.
Too many vias can also break a plane apart, as seen here where the black indicates areas of no copper. This requires careful attention in dense areas such as underneath the FPGA.
Even if you go to the trouble of having an unbroken plane, you might accidently create trouble with dense vias. Everywhere you have a via means some clearance around internal planes that the vias do not connect to. Enough vias close together will result in an effective slot in that internal plane, as in Figure 4.
This can get really troublesome if you have a split plane supplying power to the FPGA, something common in practice due to the multiple voltages required. The underside of the FPGA also tends to have a dense concentration of vias due to the signal breakout required. In my board are a number of vias for both GND and VCC-IO (3.3 V) surrounding the VCC-INT pins. These “other” vias will pierce the VCC-INT island and cause a chunk of copper to be removed from the island.
A handy option in my Altium Designer design tool is something called the “PDN Analyzer,” which helps you understand what sort of voltage drops you might see on the power distribution network (PDN). As it can be almost impossible to avoid these holes in dense boards, the PDN analyzer provides a useful resource for simulating your voltage drop and also visualizing the current density to ensure you won’t cause problems in the physical PCB. Figure 5 shows an example of the PDN visualization, where there is about a 50 mV expected drop from a 3-A current draw.
Altium Designer’s optional PDN Analyzer package can be used to verify both voltage drop and current density in a split plane situation, especially where the plane becomes punctured by vias. This gradient shows the voltage drop from the supply (bottom left) to the FPGA (upper right).
Using reasonable annular ring sizes on these vias would result in very close spacing between traces and the outer copper of the ring. A standard via places that ring on every layer of the PCB, even if there is no connection.
Using the PDN Analyzer, I was able to see some excessively high current density. This high current density was due to narrow slivers of power plane between vias that were piercing the VCC-INT island. Rearranging the vias solved the problem and avoided potential issues such as the local heating of those slivers of copper due to the high current density.
VIA TROUBLE
Piercing the power plane isn’t the only potential trouble you can have. You may also find that your FPGA package requires a more advanced (and thus expensive) PCB technology than you planned on using.
The BGA in this board is a Xilinx CSG324 package, which has a finer 0.8-mm pitch than the 1-mm pitch FTG256 package I used in my December 2015 article. This causes a bit of a problem when we go to break out the FPGA, which you can see in Figure 6. The spacing between break-out vias is too narrow to allow a 5-mil trace/space. This will create islands where we cannot break out certain balls, since we can’t route a trace between the vias.
But this assumes every layer has the same ring around the via drill hole. Thus, the solution is to (carefully) use vias with incomplete stack-ups. That is to say they do not have a full copper ring on each layer. This is shown in Figure 7, where you can see, for example, that certain vias have no connection to inner layers. Figure 7 shows how the trace in Figure 6 was successfully routed between the vias. The vias on either side of that trace have no copper ring on the associated layer.
The rings surrounding the vias on certain layers can be removed to allow a trace to pass. Here the two vias pointed at have no ring on the cyan layer (Layer 4) to allow the trace to pass between them. The vias on the upper right of the figure have both the yellow and cyan rings present, showing the standard via stack-up. The power plane layers are not shown in this figure.
It’s useful to “stub out” things you might require but are unsure about, such as adding SPI flash to your design even if planning on programming from a microcontroller. Resistor R46 can be mounted to feed the SPI flash output into the FPGA.
GIVE ME THE POWER
So far I’ve concentrated on the physical design of the board, and have skipped over the electrical design. I’ll briefly summarize some considerations around additional FPGA support resources required here.
The first thing you’ll need is a suitable power supply. The requirements here will vary drastically based on specifics of your design. For example, if you have a design with external DDR3 memory, you’ll need to supply considerably more power for the I/O drivers related to that bus compared to a simple SRAM interface.
Luckily, the FPGA vendors (such as Xilinx and Altera) provide tools to estimate the power consumption based on estimates of your design (such as number and standards of I/Os, speeds of clocks, approximate resource utilization, etc.). This lets you design an appropriate power supply without over-engineering the design.
Most likely, you’ll need a switch-mode power supply. Many different vendors provide highly reliable switch-mode power supply controllers, which by following the suggested circuit and layout can be used with great reliability. On this example board, I’m using the Alpha & Omega Semiconductor AOZ1094 and AOZ1021 switch-mode buck regulators for the VCC-INT and VCC-IO supplies, respectively. I’d used them previously on a similar design, so I simply copied that onto this board.
LOSING YOUR MIND
One other standard consideration is the FPGA configuration memory. At minimum you should always route the JTAG header out, as it makes the most reliable “first contact” for checking the board design and FPGA is working correctly. For Xilinx FPGAs, I normally use the small 2-mm header that plugs into the configuration cable, which is a Molex Milli-Grid header (part number 0878321420).
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Lately, all of my FPGA designs are configured from a bitstream downloaded over USB (known as slave serial mode). Despite this I always design a SPI FLASH memory chip onto the board, such that the FPGA could be configured to operate from a power-on bitstream if needed.
You can even mount the majority of the parts if you want, as in Figure 8. Here, by mounting resistor R46, I can enable the SPI flash output to drive the configuration DIN pin. SPI flash memory mounted like this can be configured through the JTAG programming tool, making it a very easy way for boards to power-on live.
KEEP THE BEAT
The final standard across all designs will be clock input(s). Many designs simply use an external oscillator mounted somewhere that drives a FPGA global CLK pin. You may also be able to use a clock output from a microcontroller on your board, saving the cost of an additional oscillator.
These clock signals should always be routed to a global clock pin. If you’re using the newer 7-series Xilinx products, note that the GCLK pins come in positive/negative pairs, designed to accept differential clock inputs.
If using them single-ended, you can only use the positive input. Don’t try routing a clock to the negative side! So, for example, if on your schematic you have a pin called “IO_L13P_T2_MRCC_14” and “IO_L13N_T2_MRCC_14,” you can only route a clock to the first of those two inputs.
If you have complete control over the clock input pin, you should also check for any restrictions on the global clock pins. As mentioned in my June 2016 article, “Optimizing Clock Resources in FPGAs” (Circuit Cellar 311), the “Global” in global clock input can be a little misleading. If it’s a very early prototype, it doesn’t hurt either to break out extra clock pins or to add spare oscillator pads that you don’t populate. If it turns out it’s better to input the clock to a different region, or if you need a different frequency, having the pads there makes it an easier job than trying to fly-wire something in later.
While this article has been just a quick overview, hopefully it gives you some confidence to design your own FPGA board using the latest devices. It’s possible to design and assemble a board at reasonable costs, showing it’s something that a small engineering company, or even a well-equipped amateur, is capable of doing. 
RESOURCES
A. Eadie, EMC Pre-Compliance Course, www.emcfastpass.com.
R. Lacoste, “Digital Line Terminations,” Circuit Cellar 309, 2016
C. O’Flynn, “Building an FPGA Board,” Circuit Cellar 305, 2015.
———, “Optimizing Clock Resources in FPGAs,” Circuit Cellar 311, 2016.
———, “Split Ground Plane: Example of Failing High-Speed Signals,” 2013, http://colinoflynn.com/2013/04/split-ground-plane-example-of-failing-high-speed-signals/.
———, “USB-to-FPGA Communications,” Circuit Cellar 299, 2015.
Teledyne LeCroy, Signal Integrity Academy, www.bethesignal.com.
SOURCES
AOZ1094 and AOZ1021 Switch-mode buck regulators
Alpha & Omega Semiconductor | www.aosmd.com
SAM3U Microcontroller
Microchip Technology (formerly Atmel) | www.microchip.com
Milli-Grid Header (part number 0878321420)
Molex | www.molex.com
CSG324 package Spartan-6 LX45 FPGA
Xilinx | www.xilinx.com
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • OCTOBER 2016 #315 – Get a PDF of the issue
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Colin O’Flynn has been building and breaking electronic devices for many years. He is an assistant professor at Dalhousie University, and also CTO of NewAE Technology both based in Halifax, NS, Canada. Some of his work is posted on his website (see link above).
