Motors and MCUs
Servo drives are a key part of many factory automation systems. Improving their precision and speed requires attention to fast-current loops (FCLs) and related functions. Here, Ramesh gives an overview of the functional behavior of the servo loops, using fast- current- loop algorithms, in terms of bandwidth and phase margin.
High-performance motor drives in servo control applications are expected to provide high-precision and high-bandwidth control of current, speed and position loops. They play a vital role in the control of end applications such as robotic arms, CNC machines and so forth. Because the current loop makes up the innermost control loop, it must have a high bandwidth to enable the outer speed or position loops to be faster. With that in mind, a high-bandwidth, fast-current loop (FCL) is needed in high-performance industrial servo control applications. However, the delay in control due to ADC conversion and algorithm execution limits the current controller bandwidth to about a tenth of the sampling frequency.
The major challenge in digital motor control systems is the slowing that’s caused by sample and hold (S/H) and transportation delays inside the loop between feedback sampling and the control action. In a time-critical algorithm such as the fast current loop, the latency between feedback sampling and control action, or PWM update, should be as small as possible. A minimal current loop time not only helps to improve the control bandwidth, but also enhances the inverter modulation index (M-I). A higher M-I translates into the higher phase voltage that the inverter can apply on the motor. Higher loop latency will reduce the maximum available voltage. It can also restrict the rate of current change in the motor at higher speeds, adversely affecting the controller performance.
In addition to latency considerations, there’s a need for flexibility to interface various position encoders with the control system. All this can justify the need for FPGAs and external ADCs to implement the fast-current loop. However, with the advent of new-generation Texas Instruments C2000 microcontrollers, it is now possible to replace the functionality of FPGAs and external ADCs. The MCUs can run speed and position loops with a minimal board space, thereby providing a cost-effective solution. This article outlines the evaluation of a fast-current-loop (FCL) algorithm on servo drives using the software frequency-response analysis (SFRA) method, where both FCL and SFRA are available as libraries from TI.
The speed control block diagram of a field-oriented-control- (FOC) based AC motor control system is shown in Figure 1. The current loop is highlighted here because of its critical importance to the outer loop bandwidth. For the outer loop to have a higher bandwidth, the inner loop must have a far higher bandwidth. It should be at least three times greater than the outer loop bandwidth requirement.
The major challenge in implementing the current loop lies in reducing the latencies between feedback sampling and PWM updates. In traditional control schemes, this latency is typically one sampling period, thereby delaying the control action. In other words, it leads to one sampling period of inaction to any disturbances in the loop. For a fast-current loop, this delay must be as small as possible, to improve the loop performance over the wide range of motor operating speeds. Typically, a latency of 1 µs or less is considered acceptable in many applications, as illustrated in Figure 2. This requires a controller with a fast-compute engine, a fast ADC, low-latency control peripherals and a superior control algorithm.
TI provides the algorithm for fast-current loop as a linkable library that leverages the following features in the F2837x MCU:
• 4 high-speed 12-/16-bit ADCs
• Trigonometric and Math Unit (TMU)
• Parallel processing core: Control Law Architecture (CLA)
• Enhanced PWM
• Enhanced QEP or Absolute encoder feedback
The block diagram of the FCL library with its inputs and outputs is shown in Figure 3. The Fast Current Loop Library partitions the algorithm across various accelerators to lower the PWM update latency to less than 1 µs. Further optimization is possible if the algorithm is written in assembly.
The system evaluation consists of two parts: (1) implementing FCL in two servo drives configured as motor-generator coupled to each other; and (2) performance analysis of FCL using SFRA and obtaining the loop bandwidth.
Implementing FCL consists of integrating the library inside the speed control loop. However, performance analysis and bandwidth determination need some consideration. To study the current loop bandwidth, the back EMF component of the loop needs proper decoupling or compensation—otherwise it can influence and distort the analysis. At zero speed, when there is no back EMF, the loop performance can be analyzed using frequency-response analysis methods. This can be used as a reference to verify the performance at different speeds, to see if there is any change in the controller behavior. This helps to ensure the robustness of controller implementation at various speeds.
To perform this effectively, a motor-generator set is useful. One can be controlled to hold a certain constant speed, while the other can be used as a load. The software can be built to control two motors independently, while they are coupled together as motor-generator. Frequency-response analysis can be performed on the current loop of the generator, while the other motor is controlled in constant speed mode. Because the speed is held constant by the drive motor, the generator current loop sees minimal—if any—speed jitter. This helps to obtain a frequency analysis report free of speed related jitters. The same analysis can be repeated on drive side motor too for verification.
CURRENT LOOPS COMPARED
Two sets of tests are performed on the drive—one using FCL and the other using classical current loop. The bandwidth and phase margin results obtained at different bandwidth design settings are noted for each set of tests, and the collected data are shown in Figure 4.
The group of plots at the bottom is obtained with classical control (without using FCL), and the one at the top is obtained with FCL. They indicate that without FCL, the control bandwidth is too low, and that with increasing control bandwidth, the phase margin drops drastically. When FCL is used, the controller can provide a higher bandwidth at a higher phase margin, and the reduction in phase margin with increased bandwidth is much smaller. The best performance occurs when the bandwidth is about one-sixth of the sampling frequency—where it almost behaves like deadbeat control. For frequencies beyond that, overshoots may occur. In this evaluation, the PWM carrier is 10 kHz, the sampling frequency is 20 kHz and the best performance is obtained when the control bandwidth is 3.3 kHz.
The performance analysis clearly establishes an improved control bandwidth at reasonable phase margin with fast-current loop, as verified by the SFRA tool. High-performance peripherals and accelerators help to mimic the performance of FPGA plus external ADC, to reduce the latency between feedback sampling and PWM update. The result is higher control bandwidth and higher maximum modulation index. Higher modulation index helps to increase the speed control range of the motor.
Depending on the control speed ranges of motors in target applications, the MCU is capable of controlling multiple motors in multi-axes configurations using FCL. This makes it suitable for high-end servo control applications.
Texas Instruments | www.ti.com
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • NOVEMBER 2018 #340 – Get a PDF of the issueSponsor this Article