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Designing Combinational Circuitry

Written by Wolfgang Matthes

Employing Tiny Logic

Tiny or little logic components belong to the staple portfolio of semiconductor manufacturers. For some special purposes, they offer compelling advantages. Components that are barely visible on the printed circuit board connect, for example, ASICs to microcontrollers (MCUs), or allow a reduction in the pin count and hence the cost of the more flashy ICs. Therefore, designing gate by gate is not an outdated art. It is, however, different from the gate-level design of the past. Here we give an overview of components, design rationales, and particular solutions.


  • How can I employ tiny logic components in my design?
  • What are good combinational circuitry design principles?
  • What are different tiny logic components and what are their functions?
  • Tiny logic combinational circuitry components

Sometimes, digital or logic design tasks require more than one gate, but are not so complex that a CPLD or even an FPGA is deemed necessary. When small-scale digital design is only an occasional challenge, encompassing only a minor part of the total circuitry, one may have concerns about the expenditures for a CPLD/FPGA integrated development environment (IDE), programming equipment, and so on. Thus, it may be expedient to resort to traditional logic design. This is not just a matter of tinkering. On the contrary, elementary logic circuitry is also used in large-volume fields of use like automotive systems. Consequently, semiconductor manufacturers offer a broad portfolio of appropriate devices (Figures 1 to 5) [1-15].

FIGURE 1 
Buffers and inverters. One, two, or three of those devices are housed in one IC package (single, dual, or triple devices).
FIGURE 1
Buffers and inverters. One, two, or three of those devices are housed in one IC package (single, dual, or triple devices).
FIGURE 2 
Gates with two inputs. There are single and dual gates.
FIGURE 2
Gates with two inputs. There are single and dual gates.
FIGURE 3 
Gates with three inputs. In tiny packages, only single devices are available.
FIGURE 3
Gates with three inputs. In tiny packages, only single devices are available.
FIGURE 4 Two examples of somewhat more complex devices. Above a 2-to-1 data selector/multiplexer with Schmitt-trigger inputs (74AUP1T157), below a 2-to-4 line decoder (74LVC1G139). The similar multiplexer 74AUP1T158 has an inverted output.
FIGURE 4
Two examples of somewhat more complex devices. Above a 2-to-1 data selector/multiplexer with Schmitt-trigger inputs (74AUP1T157), below a 2-to-4 line decoder (74LVC1G139). The similar multiplexer 74AUP1T158 has an inverted output.
FIGURE 5 
A few of the tiny IC packages (not to scale).
FIGURE 5
A few of the tiny IC packages (not to scale).

Packages are, so to speak, a science in itself. There are many package types around, the manufacturers have different designations, suffixes, and trademarks, and they are always busy inventing something new, making things smaller and smaller. The latest types are indeed very tiny. They have no leads, and the backsides are covered with solder contacts. To give a first impression of what we’re talking about, Figure 5 shows a few examples. Beyond that, refer to the manufacturer’s catalogs, application notes, datasheets, and cross-reference tables (see, for example, [2-4] and [7-14]).

The “tiny” or “little” IC series comprise sets of different gates: AND, NAND, OR, NOR, XOR, and XNOR. Additionally, there are multipurpose devices that can be configured to perform the desired logic function. So, the problem of implementing all the combinational functions by a single type of gate does not exist (in contrast to the distant past, where designers had to get by with only NANDs (TTL) or NORs (ECL)). Designing with such components could be dubbed trickery in the small. What is taught in introductory digital engineering courses may not be that helpful. Therefore, we will not proceed by explaining Karnaugh-Veitch diagrams and the like. Devices with three-state outputs, flip-flops, analog switches, and so on we have omitted here. Instead, we will concentrate on straightforward combinational circuits.

A FEW APPLICATION EXAMPLES

Tiny logic solves small or straightforward logic tasks on the spot. There is no talk of implementing arithmetic-logic units (ALUs) or finite state machines (FSMs).

A simple application is patching, as illustrated in Figure 6. A complex IC generates an output signal whose behavior fits well with an input of another highly integrated device. Unfortunately, the signal is generated active-Low, but the input of the receiving IC is active-High. A tiny inverter is the most straightforward solution to this problem.

Figure 7 depicts a long signal trace running across the board. Such traces may pick up noise and may cause the signal edges to deteriorate. The integrated circuit shown here needs, however, a clean signal with steep edges. Think, for example, of a clock or reset input. A tiny buffer, placed in the near vicinity, would solve the problem. The alternative shown concerns diagnostics and PCB testing. Here, a tiny multiplexer allows for the injection of a diagnostic signal (think of clock pulses excited by a tester or a service processor) if the circuitry is switched to a diagnostic mode.

The example in Figure 8 concerns an application where direct-acting (that is, non-programmable) hardwired logic is a mandatory requirement. In case of an emergency, signals are to be brought to determined levels. All further activities are to be inhibited. Low levels can be enforced by AND gates, high levels by OR gates.

The package contributes crucially to the cost of a complex integrated circuit. So it’s understandable to want to get by with fewer pins and a package that’s less costly to purchase and process. Occasionally, external circuitry can save on the required number of pins considerably, as illustrated in Figure 9.

For example, some or even many sensor signals may be OR-ed together to trigger an interrupt in a microcontroller (MCU) (Figure 10a). A further example is detecting conditions on signal lines for conditional branching or to trigger interrupts. For that, we must implement so-called product terms. That means AND-ing together the particular signals, either true or inverted (Figure 10b).

To house this kind of circuitry, we may think of a CPLD or even a low-cost FPGA. Occasionally, this approach is recommended by manufacturers of programmable logic [46-48]. The obvious advantages are that functional complexity is not restricted, and you can master such tasks without being a seasoned digital designer, at least in most cases. (I recommend resorting to the Verilog hardware description language (HDL) and leaving the rest to the IDE.) The benefits of tiny logic appear if only straightforward combinational functions are to be implemented. Then you will get by without HDL and IDE at all.

Figure 11 illustrates a further advantage. Imagine a somewhat larger PCB with sensors (S) or other signal sources spread over the total real estate. When all those signals are to be OR-ed or AND-ed by a single CPLD or FPGA, all the signal lines have to be routed to this device. Therefore, it could make sense to also distribute the combinational circuitry over the PCB, especially if cost is a primary concern and the number of PCB layers should be kept as low as possible.

FIGURE 6 
A tiny inverter adapts an active-Low output to an active-High input.
FIGURE 6
A tiny inverter adapts an active-Low output to an active-High input.
FIGURE 7 
Lengthy traces impede signal integrity. A tiny device in the near vicinity ensures a clean signal at the IC’s input. If the signal’s edges are deteriorated, a buffer with a Schmitt-trigger input is the obvious choice. The multiplexer beyond (the device shown in Figure 4) is an alternative if diagnostics or PCB testing are to be supported.
FIGURE 7
Lengthy traces impede signal integrity. A tiny device in the near vicinity ensures a clean signal at the IC’s input. If the signal’s edges are deteriorated, a buffer with a Schmitt-trigger input is the obvious choice. The multiplexer beyond (the device shown in Figure 4) is an alternative if diagnostics or PCB testing are to be supported.
FIGURE 8 
Tiny gates enforce particular signal levels in case of an emergency.
FIGURE 8
Tiny gates enforce particular signal levels in case of an emergency.
FIGURE 9 
Particular conditions or bit patterns on signal lines are to be detected. It could be done by a decoder in the FPGA or ASIC or by comparing read-in bit patterns by software. This, however, requires connecting all signal lines, thus wasting precious I/O pins (a). If the conditions are detected by external circuitry, only one or a few pins are needed. Thus we could get by with an MCU, FPGA, or ASIC in a smaller package (b).
FIGURE 9
Particular conditions or bit patterns on signal lines are to be detected. It could be done by a decoder in the FPGA or ASIC or by comparing read-in bit patterns by software. This, however, requires connecting all signal lines, thus wasting precious I/O pins (a). If the conditions are detected by external circuitry, only one or a few pins are needed. Thus we could get by with an MCU, FPGA, or ASIC in a smaller package (b).
FIGURE 10 
An apparent advantage of the external combinational circuits is that we could get by with an MCU in a cheaper package (that is, one with fewer pins).
FIGURE 10
An apparent advantage of the external combinational circuits is that we could get by with an MCU in a cheaper package (that is, one with fewer pins).
FIGURE 11 
Tiny logic may be dispersed over the printed circuit board (PCB). Here, sensors (S) are shown. They are to be OR-ed together to trigger interrupts in the MCU. When done in a CPLD, for example, all sensor signals must be routed to this device. When spreading OR gates in the vicinity of the sensors, only a few traces need to be run to the MCU.
FIGURE 11
Tiny logic may be dispersed over the printed circuit board (PCB). Here, sensors (S) are shown. They are to be OR-ed together to trigger interrupts in the MCU. When done in a CPLD, for example, all sensor signals must be routed to this device. When spreading OR gates in the vicinity of the sensors, only a few traces need to be run to the MCU.
DESIGNING WITH TINY LOGIC

Our primary design challenges are twofold. The first is to choose tiny components wisely. The second consists of cascading such components so that more, or even many, input signals can be attached. For both goals, the sharpest tool in our box is DeMorgan’s law (Figure 12). There is an uncountable number of sources that deal with Boolean algebra and basic gate-level design. More often than not, however, Boolean functions are not treated as tools for problem-solving but solely as objects of minimization. I recommend looking first into the technical documentation the semiconductor manufacturers provide (like [4] or [52]), and not to begin with college-level textbooks.

Capturing the problem and understanding the design task: The problems to be solved are not that complicated. Nevertheless, they must be understood in their intricate details. A well-proven approach is to describe the problem as painstakingly as possible using the terms AND, OR, and NOT. This way, we will obtain at first colloquial and then formalized Boolean expressions. They are to be implemented by our tiny components. Mostly, it could be done best by assembling the combinational circuits step by step from small basic gates, without dealing with two-level canonical forms, Karnaugh-Veitch diagrams (K-maps), and the like. A well-proven overall approach is to first solve the pure logical design problem, assuming that all types of tiny devices may be applied. The levels and supply voltages, the IC families, packages, and so on are dealt with in a second pass.

Logic levels and signals: Propositional logic knows only two values. Applying them to digital design seems to be the most straightforward thing on earth. Those values are, however, to be assigned to the problem to be solved, and it’s easy to mix something up, causing annoying design errors. So be careful and better look once more. In the beginning, we will assume that all is without a hitch. The supply voltage (VCC), the Low and High levels, and the IC families fit well together. The problems we will discuss later.

The logic levels are physical facts. If a level is nearer to minus infinity (–∞), it is called Low; if nearer to plus infinity (+∞), it is called High.

Propositional logic is concerned with truth. George Boole has equated truth with 1 and falsehood with 0. In addition, 0 and 1 are the digits of binary numbers. If the 0 is represented by the Low level and the 1 by the High level, we speak of positive logic. The opposite assignment is called negative logic.

Generally, there are two kinds of signals. The first carries binary digits, ones or zeros. They have nothing to do with truth, falsehood, activity, idleness, and the like, but are simply two values of equal significance. Signals of the second kind exert activities. The logic levels represent two states, idle (or off or deasserted), and active (or on or asserted). In this regard, we speak of signals that are active-Low or active-High.

As a first example, Figure 13 shows how two active-Low signals can be combined by AND, NAND, OR, and NOR gates. If the output is to be active-Low, an AND gate acts as an OR (Figure 13a), and an OR gate as an AND (Figure 13b). If the output is to be active-High, a NAND is to be used instead of the AND (c), and a NOR instead of an OR (d).

In one of the earliest applications of tiny logic, the AND gate of Figure 13a is employed to turn the venerable 8051 microprocessor (MPU) into a von Neumann machine (Figure 14). Architecturally, the 8051 has separate memories for programs and data (Harvard architecture). It is obvious to store programs in the ROM and data in the RAM. In some applications, however, it is desirable to have a unified memory (von Neumann architecture). PSEN# signalizes that instructions are to be fetched. RD# signalizes that data bytes are to be read. To get access to both memories for instructions as well as for data, a joint output enable (OE#) signal is generated by OR-ing both low-active signals. To select the ROM or the RAM, the highest-order address bit is used here, requiring, in addition, a tiny inverter.

Positive and negative logic: An AND in positive logic corresponds to an OR in negative logic and vice versa. The same correspondence applies to NAND and NOR, as well as to XOR and XNOR (Figure 15).

Gates with inverted inputs: If the inputs of a gate are inverted or if inverted signals are applied, the gate’s function will change according to DeMorgan’s law, as depicted in Figure 16.

XOR and XNOR: XOR stands for exclusive OR; XNOR is an XOR with the output inverted. An XOR gate with two inputs signalizes inequality, and a corresponding XNOR signalizes equality. In other words, the XNOR behaves as a single-bit equality comparator. A positive logic XOR corresponds to a negative logic XNOR and vice versa. Both gates can be operated as controllable inverters (Figure 17). The output of an XOR with an arbitrary number of inputs signalizes a one if the number of ones at the inputs is odd (odd parity).

Cascading: Cascading means composing a gate with many inputs from gates having few inputs. Non-inverting gates of the same type can be cascaded easily (Figure 18a). To cascade inverting gates, additional inverters must be interspersed (Figure 18b). With the comprehensive assortment of gate types available nowadays, the most straightforward solution is to combine non-inverting and inverting gates (Figure 18c).

There are two basic topologies to cascade gates: the daisy chain (Figure 19) and the inverted tree (Figure 20). For a particular number of inputs, both need the same number of gates. Only the propagation delay is different. In a daisy chain, it increases linearly with the number of cascaded gates. In the tree, it increases logarithmically. If propagation delay is not that important, you may prefer the topology that is most expedient for routing.

FIGURE 12 
DeMorgan’s law describes the so-called duality between AND, OR, the inversion of the outputs, and the inversion of the inputs. AND and OR can be swapped against each other, provided non-inverted signals are inverted and vice versa.
FIGURE 12
DeMorgan’s law describes the so-called duality between AND, OR, the inversion of the outputs, and the inversion of the inputs. AND and OR can be swapped against each other, provided non-inverted signals are inverted and vice versa.
FIGURE 13 
How basic gates act on active-Low signals.
FIGURE 13
How basic gates act on active-Low signals.
FIGURE 14
Turning the 8051 into a v. Neumann machine where instructions and data are located in the same address space can be done by two tiny devices, an AND gate, and an inverter.
FIGURE 14
Turning the 8051 into a v. Neumann machine where instructions and data are located in the same address space can be done by two tiny devices, an AND gate, and an inverter.
FIGURE 15 
Positive (above) and negative (below) logic.
FIGURE 15
Positive (above) and negative (below) logic.
FIGURE 16 
Inverted inputs will alter the function.
FIGURE 16
Inverted inputs will alter the function.
FIGURE 17 
Some particular properties of the XOR and XNOR functions.
FIGURE 17
Some particular properties of the XOR and XNOR functions.
FIGURE 18 
Extending the number of inputs by cascading.
FIGURE 18
Extending the number of inputs by cascading.
FIGURE 19 
Cascading by daisy-chaining.
FIGURE 19
Cascading by daisy-chaining.
FIGURE 20 
Cascading by connecting the gates according to an inverted-tree topology.
FIGURE 20
Cascading by connecting the gates according to an inverted-tree topology.

By using NAND and NOR gates and applying DeMorgan’s law, you can implement AND, OR, NAND, and NOR functions with an arbitrary number of inputs (Figure 21 and Figure 22). A NOR corresponds to an AND of inverted signals. An AND with many inputs can thus be implemented with NAND gates whose outputs are connected to a NOR gate. A NAND corresponds to an OR of inverted signals. An OR with many inputs can thus be implemented by NOR gates whose outputs are connected to a NAND gate. XORs are cascaded like non-inverting gates. A wide XNOR can be built from cascaded XORs with an inverter downstream.

To implement gate functions with even more inputs, cascade an appropriate number of the circuits shown in Figure 21 (Figure 22). If all gates have two inputs, such so-called DeMorgan trees may be built with four, 16, 64 (and so on) inputs. Using gates with three inputs, the smallest DeMorgan tree would have nine inputs. A two-level tree (similar to Figure 22) would have 81 inputs, and so on. (See, for example, [52] for a comprehensive description of DeMorgan trees.)

AND-ing and OR-ing true (not inverted) and inverted signals: Figure 23 depicts the problem together with the solution. Some of the input signals are attached directly, some are to be inverted. Typical applications are to detect particular conditions, like a bit pattern on a data bus and some control signals on, some off, or to combine sensor signals, some of them active-High, others active-Low. The solution follows from DeMorgan’s law. A NOR acts as an AND of inverted variables, and a NAND as an OR. Thus, all input signals to be inverted are connected to a NOR or NAND gate, respectively.

Expanding with diodes: I discussed diode gates in my previous article (“Solving Level-Translation and Logic Problems: Using Discrete Components,” Circuit Cellar 395, June 2023) [37]. Here, where only CMOS buffers or gates are to be driven, the static load current may be neglected. Occasionally, diodes could be a viable solution for expanding the number of inputs (Figure 24). They are small and cheap, and they need no power supply (GND/VCC) traces on the PCB.

The approach has, however, some caveats. A diode AND increases the Low level, and a diode OR decreases the High level by one forward voltage drop (VF). Because of the low voltages, we cannot be as generous as in a 24V environment (as done in [37]). The output levels of the diode gates must comply with the input specification of the downstream device. The low level must be well below VILmax, the high level well above VIHmin. Due to their low forward voltage drop, Schottky diodes are an obvious choice. On the other hand, if there are more than a few diodes wired together, their reverse current could be a problem. As a rule of thumb, Schottky diodes could work in CMOS environments with supply voltages well above 2V. The example in Figure 24 illustrates that for a supply voltage (VCC) of 2.5V and a VF of approximately 0.4V, the levels of the Y output come dangerously near the specified ranges of input levels of the downstream device. When contemplating this solution, strive to keep VF low by selecting appropriate components. Small-signal Schottkys may be a good choice [33, 34]. They are also available in packages containing, for example, two diodes (isolated or with the cathodes or anodes connected). Bus termination arrays contain more diodes, but their VF may be too high [35]. RL is to be dimensioned according to (VCC – VF)/IF. Setting the diode’s forward current IF is a compromise: not too high to keep VF low, but high enough to ensure proper diode operation and sufficiently fast charging and discharging of the parasitic capacitances (say, between 0.1mA and 1mA). The rise and fall times should be within the limits of the downstream circuit’s specification. Beware that Schmitt-trigger inputs may be no remedy here because their high-to-low threshold voltage is considerably lower than VCC/2. So, it’s wise not to neglect a worst-case analysis.

Logic by wiring: Open-drain outputs can be wired (dotted) together (Figure 25). If at least one of the output transistors is switched on, the output level will be low. If all transistors are switched off, the output level depends on the voltage drop across the load resistor. Properly dimensioned, the output voltage will remain in the region of the High level. In a nutshell: Low is caused by the transistor switched on, and High by the load resistor if the transistor is switched off. The term “wired-OR” is widely known. It may be, however, somewhat misleading. It is only correct when we speak of negative logic or signals that are active-Low. If the output is active-High, the circuit acts as a NOR. Concerning positive logic or active-High inputs, the circuit behaves like an AND.

FIGURE 21 
Making good use of DeMorgan’s law. a) shows an AND, b) an OR with four inputs each. NAND  and NOR functions are obtained by not inverting the output.
FIGURE 21
Making good use of DeMorgan’s law. a) shows an AND, b) an OR with four inputs each. NAND and NOR functions are obtained by not inverting the output.
FIGURE 22 
An example of a DeMorgan tree. The AND shown here has 16 inputs. It consists of two levels or layers of circuits according to Figure 21a. A similar structure, built with circuits according to Figure 21b, would yield a corresponding OR gate.
FIGURE 22
An example of a DeMorgan tree. The AND shown here has 16 inputs. It consists of two levels or layers of circuits according to Figure 21a. A similar structure, built with circuits according to Figure 21b, would yield a corresponding OR gate.
FIGURE 23 
True and inverted signals are to be AND-ed or OR-ed. Resorting to DeMorgan’s law, we can save on inverters and get by with fewer components. a) shows how to implement a minterm or product term, b) how to implement a maxterm.
FIGURE 23
True and inverted signals are to be AND-ed or OR-ed. Resorting to DeMorgan’s law, we can save on inverters and get by with fewer components. a) shows how to implement a minterm or product term, b) how to implement a maxterm.
FIGURE 24 
Diode gates. a) AND; b) OR. The example on the right shows the influence of the diode’s forward voltage, assuming worst-case output voltages of the upstream gates and a VF of 0.4V. For the level specifications of the 2.5V logic, see Figure 34.
FIGURE 24
Diode gates. a) AND; b) OR. The example on the right shows the influence of the diode’s forward voltage, assuming worst-case output voltages of the upstream gates and a VF of 0.4V. For the level specifications of the 2.5V logic, see Figure 34.
FIGURE 25 
Wired (dotted) logic. a) Dotted active-High signals yield an AND function. b) If the dottet signals are active-Low, a NOR results (colloquially called the wired-OR). c) The AND function can be implemented by dotting AND gates. Inverting the output yields a NAND. d) Dotting NAND gates results in an AND-OR-INVERT (AOI) Function. Inverted, it is the sum-of-products (SOP) function.
FIGURE 25
Wired (dotted) logic. a) Dotted active-High signals yield an AND function. b) If the dottet signals are active-Low, a NOR results (colloquially called the wired-OR). c) The AND function can be implemented by dotting AND gates. Inverting the output yields a NAND. d) Dotting NAND gates results in an AND-OR-INVERT (AOI) Function. Inverted, it is the sum-of-products (SOP) function.

In tiny-logic IC series, the assortment of open-drain devices comprises buffers (non-inverters), inverters, NAND gates, and AND gates. The outputs are mostly specified for voltages higher than VCC (for example, up to 3.6V or even above 5V). Therefore, such components may also be used for level translation. Combinational functions with many inputs can be implemented by wiring together (dotting) an appropriate number of open-drain components. To implement a wired-AND, active-High-signals are to be attached via AND gates or non-inverters, active-Low signals via inverters. The wired-OR function results if active-Low signals are attached via non-inverters and active-High signals via inverters. Strictly speaking, it is, however, a NOR because each active signal will enforce a Low output. Dotted NAND gates yield an AND-OR function with an inverted output, the so-called AND-OR-INVERT (AOI) function.

Dimensioning the load Resistor RL: In general, this problem has been discussed in my previous article [37]. Here, where only CMOS buffers or gates are to be driven, the static load current may be neglected. More significant is that the Low-to-High transitions are not too slow. This depends on the RC time constant. Therefore, RL should be as low as possible. As a rule of thumb that leaves a sound margin, you may spend half of the rated Low-level output current IOL of a driving upstream device. Thus, RL will be calculated according to VCC divided by half of the datasheet value of IOL. You may also contemplate getting by with a lower current and compensate for the less steep Low-to-High edges by a downstream Schmitt-trigger.

A straightforward example: Imagine a PCB similar to Figure 11 and assume that 20 sensor outputs are to be OR-ed to excite an interrupt input of an MCU. Let’s begin with active-High sensor outputs. When cascading OR gates with two inputs, 19 devices would be required. A diode-OR would require 20 diodes, the load resistor, and a buffer (with a Schmitt-trigger input, if appropriate). A wired-OR would require 20 open-drain inverters, the load resistor, and the final buffer (with a Schmitt-trigger input). If all sensor outputs are active-Low, the desired OR function can be implemented by cascading AND gates, by a diode-AND, or by a wired-AND built with open-drain non-inverters. If there are sensor outputs of both types, an appropriate solution should be found by making good use of DeMorgan’s law. The wired-OR is the most straightforward solution because it is only necessary to select appropriate open-drain buffers, that is, non-inverters for the active-Low and inverters for the active-High sensors. Sensors with active-Low open-drain outputs may be wired without additional buffering, provided their output specifications permit.

CONFIGURABLE LOGIC

Semiconductor manufacturers offer some types of tiny configurable gates that can be turned into inverters, buffers, ANDs, ORs, and so on simply by connecting the pins appropriately to signals, ground (= Low), or the supply voltage (= High). Such components (configurable multiple-function gates) can be used wherever straightforward combinational functions are required. They combine some functions that are often needed. In many applications, a configurable gate replaces two or even more single gates. Another advantage is that they can substitute single gates and so reduce the inventory. We begin with two straightforward devices, shown in Figure 26. Occasionally, such a 3-input function (AND-OR or OR-AND) will come in handy. For example, an AND-OR could be the last device downstream of cascaded gates implementing a sum-of-products (SOP) function (like A ⋅ B ∨ C ⋅ D ⋅ E ∨…). Beyond that, the devices can substitute AND gates, OR gates, and buffers. Because they lack inversion, their versatility is, however, somewhat restricted.

The theoretical foundation of the more advanced configurable devices are so-called lattices of Boolean functions. Such a lattice results from a single Boolean function by feeding each input with a signal, an inverted signal, a Low level, or a High level. If the original function has n inputs, we may imagine the entire lattice described given by 4n truth tables corresponding to all the combinations mentioned above. The obvious quick-and-dirty approach is to try out all combinations. (Yes, complexity of the order 4n is far from being quick, and the theory provides more elegant approaches.) The real trick is to find universal Boolean functions whose lattices contain as many usable functions as possible. Additional combinational functions result from making use of DeMorgan’s law. But you can’t have everything at once. The manufacturers are primarily concerned with getting by with a single package for many typical applications that is also as small as possible.

The really universal component for all possible functions of two variables would be a 4-to-1 multiplexer. That would, however, require a larger package with at least 9 pins (including GND and VCC). According to Boolean lattice theory, to be fully universal occasionally requires inverting input signals. To avoid separate inverters, the manufacturers offer some devices in pairs, with the output and one of the inputs either non-inverted or inverted (Figure 27). Figures 28 to 30 show a few configuration examples. For more details and exhaustive descriptions, we refer to the corresponding datasheets (for example, [25-30]).

The pair 1G57/1G58 has an AND gate with two inverted inputs. The corresponding AND gate of the pair 1G97/1G98 has only one inverted input. With the 1G57/1G58 you can build XOR and XNOR gates, but not a 2-to-1 multiplexer; with the 1G97/1G98 it is the other way around. The 1G99 is basically a 1G97 enhanced with an XOR gate and tri-state output. The functions of the 1G97 or 1G98 can be emulated by wiring the XOR input D to Low or High, respectively. In addition, the circuit can be configured as an XOR or XNOR gate.

FIGURE 26 
Two straightforward multipurpose devices [31] [32].
FIGURE 26
Two straightforward multipurpose devices [31] [32].
FIGURE 27 
Examples of configurable multiple-function gates. They have Schmitt-trigger inputs (that are not shown here).
FIGURE 27
Examples of configurable multiple-function gates. They have Schmitt-trigger inputs (that are not shown here).
FIGURE 28 
Configuration examples (1). The 1G57 [26]. The 1G58 [27] implements the inverted function.
FIGURE 28
Configuration examples (1). The 1G57 [26]. The 1G58 [27] implements the inverted function.
FIGURE 29 
Configuration examples (2). The 1G97 [28]. The 1G98 [29] implements the inverted function.
FIGURE 29
Configuration examples (2). The 1G97 [28]. The 1G98 [29] implements the inverted function.
FIGURE 30 
Configuration examples (3). The 1G99 [30]. The tri-state output is not shown here. To enable the output, connect OE to GND.
FIGURE 30
Configuration examples (3). The 1G99 [30]. The tri-state output is not shown here. To enable the output, connect OE to GND.
UNIVERSAL LOGIC

What we strive for are universal or general-purpose integrated circuits to implement arbitrary combinational functions. In contrast to CPLDs and FPGAs, however, they should do without programming.

The theoretical foundation is Boole’s and Shannon’s expansion theorem. On n signal lines, 2n different combinations of Low and High levels may occur. For each of those combinations, an AND gate—in other words, a product term—is provided. Each of the 2n AND gates has an additional control input. If this input is active, the AND gate will contribute to the function to be implemented; otherwise, it will remain idle. All AND gates are OR-ed together (Figure 31). To implement a particular function, we begin with its truth table. The control inputs of all AND gates that correspond to ones in the result column are connected to High, the remaining to Low.

An ensemble of 2n AND gates, one for each bit pattern, is essentially a decoder. So let us look for basic types of components in which 2n product terms are readily decoded. There are three such basic types, the binary (1-out-of-n) decoder, the multiplexer, and the addressable memory. Integrated decoders (like the venerable 74×138) contain only the AND gates. OR-ing is to be done outside. Thus, for practical reasons, the decoder-based solution may be omitted here.

The multiplexer as a universal combinational building block: The multiplexer is a combination of a data selector and an address decoder. A multiplexer with n address inputs selects one of the data inputs to be gated through to the output. Thus, one can use a 2n-to-1 multiplexer to implement any combinational function of n variables. It requires only wiring the data inputs to Low or High, according to the result column of the corresponding truth table (Figure 32). Thus, the multiplexer becomes a small read-only memory (ROM). In some FPGA families, the logic cells are implemented this way. To be programmable, the multiplexer inputs are attached, for example, to the flip-flops of a shift register or to flash memory cells.

Unfortunately, the series of tiny logic components contain no multiplexers with a useful number of inputs (4, 8, or even 16). Therefore, you must resort to components in larger packages. Occasionally, analog multiplexers may work, too. If break-before-make behavior is not guaranteed, I recommend not wiring the inputs directly to VCC but applying the High voltage via a pull-up resistor to limit eventual shoot-thru currents.

The addressable memory—a universal combinational building block: The memory cells are selected by addressing. n address bits correspond to 2n memory cells. Referring to the expansion theorem, the address decoder corresponds to the AND gates, the stored bits correspond to the control inputs, and the bit line implements the OR function. Thus, implementing a combinational function requires nothing more than storing the result column of the truth table.

The address inputs are connected to the input signals; the memory cells are filled with ones or zeros according to the truth table. In this way, any combinational function can be implemented, limited only by the storage capacity.

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In some FPGA families, the logic cells contain small RAMs, the so-called lookup tables (LUTs), to implement the combinational functions. Larger FPGAs also contain dedicated RAM structures, like distributed RAMs (that are LUTs operated as addressable RAMs instead of combinational circuits) and block RAMs. In an example LUT, a RAM has a storage capacity of 64 bits. Hence it can accommodate a combinational function of 6 inputs. Dedicated RAMs can be configured for different word lengths, for example, 16k x 1, 8k x 2, 4k x 4, and so on. A 16k x 1 block RAM could accommodate a combinational function of ld 16k = 14 inputs.

Outside the FPGAs, the principle of stored truth tables can be implemented by ROMs with an asynchronous memory interface, thus limiting the number of inputs between, say, 8 to 20. Here we take it as a matter of course that we want to get by with a simple design and low cost.

The idea may occur to let a ROM absorb some combinational functions that otherwise would be spread over the PCB (Figure 33). There is, however, a caveat. Memories with an asynchronous interface are internally clocked devices. They have sequencers built-in that detect when an address or control signal changes its level. Then they start a new access cycle. In the course of this cycle, the data outputs may become temporarily unstable. These oscillations affect all data outputs, regardless of the combinational function they belong to. Think, for example, of an AND function with the inputs A, B, C, and other functions depending on input signals D, E, F, and so on. Implemented with gates, the AND depending on A, B, C will not be affected if, for example, the signal E switches. In the ROM implementation, however, the AND output may show pulses, although the AND function does not depend on the input signal that has changed. On the other hand, ROM-based lookup tables are an expedient solution for FSMs, code conversion, trigonometric functions, and so on. What all such applications have in common is that the stored words and hence the output signals belong together and are subject to synchronous operation.

Figure 31
Boole’s and Shannon’s expansion theorem explained. How an arbitrary Boolean function is mapped to a universal sum-of-products (SOP) function.
Figure 31
Boole’s and Shannon’s expansion theorem explained. How an arbitrary Boolean function is mapped to a universal sum-of-products (SOP) function.
Figure 32
A Boolean function of three variables implemented by a multiplexer. Its address decoder acts as the decoder depicted in Figure 31. Suitable devices are 74x151 8-to-1 multiplexers or 8-channel analog switches, like the NX3L4051 [36]; this device guarantees break-before-make, so the inputs may be connected directly to VCC.
Figure 32
A Boolean function of three variables implemented by a multiplexer. Its address decoder acts as the decoder depicted in Figure 31. Suitable devices are 74×151 8-to-1 multiplexers or 8-channel analog switches, like the NX3L4051 [36]; this device guarantees break-before-make, so the inputs may be connected directly to VCC.
FIGURE 33 
A historical example of a ROM housing the truth tables of some combinational functions. Thus, it substitutes a considerable number of gates. Some of the Boolean equations are shown here, as they have been entered into the development system. However, as straightforward as the design idea seems, there are some gotchas to observe (which I had—decades ago—learned the hard way).
FIGURE 33
A historical example of a ROM housing the truth tables of some combinational functions. Thus, it substitutes a considerable number of gates. Some of the Boolean equations are shown here, as they have been entered into the development system. However, as straightforward as the design idea seems, there are some gotchas to observe (which I had—decades ago—learned the hard way).

Why not use an MCU?: Since the advent of the microprocessor, emulating combinational circuitry has occasionally been a topic in application notes [49-51]. When microseconds do not matter, it could be a viable approach because programming MCUs is a much more widespread skill than CPLD/FPGA design. Moreover, there is no need to purchase new development software, programming equipment, and so on.

The most straightforward approach would be to store the truth tables and let the MCU act like a ROM addressed by the input signals (only slower, of course). Such a program must read the input signals, assemble the memory address, read the addressed truth table entry, and emit the output signals. Bit processors, digital simulators, or even fully-fledged Boolean machines belong to the more demanding projects.

SOME GENERAL DESIGN CONSIDERATIONS

Selecting the logic family: The components must fit into the overall design. Above all, it relates to the supply voltage and the logic levels (Table 1 and Figures 3435). Additional stipulations to which we (as designers) must comply may concern the IC family, power consumption, speed, packages, soldering processes, testability guidelines, and so on.

When the gates are to be used in a circuit with different supply voltages and logic levels, appropriate level-translation solutions are to be found. For some design challenges, well-suited components are readily available. So skim first the catalogs and selection tables (on the Internet) before trying to find a tricky solution on your own.

Partial power down: A problem may occur when the supply voltage of particular functional units is switched off, for example, to reduce power consumption. Our gates could be without power in an otherwise powered environment or vice versa. Voltages at the inputs of conventional CMOS devices powered off (that is, with a VCC of 0V) may cause short-circuit currents to flow. Provisions to prevent this are called IOFF protection. Most of the low-voltage logic families have this feature (as mentioned in Table 1).

Overvoltage-tolerant inputs: Overvoltage/input tolerance means that the input voltage VIN may rise beyond the supply voltage VCC. Typically, the limit is the rated maximum supply voltage.

Voltage-level translation: Let us assume a particular supply voltage (VCC). If the input voltage is lower, you need a compliant device, or you will have to interpose a level-translation circuit. If the input voltage is higher, you should check whether your logic family tolerates it (Table 2Figure 36). Otherwise, you may resort to level-translation devices or try some trickery, like current-limiting via series resistors ([4] [40]).

FIGURE 34 
Logic level specifications at a glance (some minor differences neglected). TTL and 5-V CMOS are shown for reference.
FIGURE 34
Logic level specifications at a glance (some minor differences neglected). TTL and 5-V CMOS are shown for reference.
FIGURE 35 
Basic requirements for output and input levels. The downstream device should see definite Low and High levels even when noise, ground bounce, and the like are present. So, leave reasonable margins for the maximum Low and the minimum High levels.
FIGURE 35
Basic requirements for output and input levels. The downstream device should see definite Low and High levels even when noise, ground bounce, and the like are present. So, leave reasonable margins for the maximum Low and the minimum High levels.
TABLE 1 
Logic families comprising tiny gates (according to [2]).
TABLE 1
Logic families comprising tiny gates (according to [2]).
TABLE 2
Voltage-level translation by tiny devices (according to [45]).
TABLE 2
Voltage-level translation by tiny devices (according to [45]).
FIGURE 36
A few hints on how to solve level-translation problems.
FIGURE 36
A few hints on how to solve level-translation problems.

General design rules: They are to be followed even when the digital design task seems straightforward. Semiconductor manufacturers provide ample literature to be studied ([52-59] are only a few examples). The most basic rules concern unused inputs, ground and power supply routing, and bypass capacitors. Gross errors that beginners sometimes commit are leaving unused inputs open, letting the auto-router handle the ground and VCC traces like signals, and locating the bypass capacitor far away from the integrated circuit, perhaps in the opposite corner of the PCB.

Testability: When designing in earnest, that is, for manufacturing in series, this aspect should not be neglected. Especially if you contemplate somewhat tricky solutions, like diode gates, open-gate outputs, or universal logic based on multiplexers, ROMs, or even MCUs, you should team up early with the test people.

SUMMARY AND SUGGESTIONS

Unassuming tiny components still play a significant role. They support sophisticated MCUs, FPGAs, and ASICs. In some design projects, where only minor digital problems are to be solved, they may allow to get by without programmable logic, like a CPLD or an FPGA, components which would require you to purchase programming devices and development software. Here we gave an overview of tiny gates and some characteristic peculiarities of designing with them. Furthermore, we discussed basic principles of configurable and universal logic devices. The proposals of substituting gates with ROMs and even MCUs seem to defy our intent not to program. Our excuse is that such components are less costly than FPGAs and that employing them requires only run-of-the-mill computer programming skills without being familiar with digital design, hardware description languages, and CPLD/FPGA programming. The programmable universal Boolean machine is a topic in itself (to be dealt with later). 

REFERENCES
Guides and manuals:
[1]          Logic Guide 2017. SDYU001AB. Texas Instruments, 2017.
https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf?ts=1689165284559[2]          Little Logic Guide 2018. SYCT29G. Texas Instruments, 2018.
https://www.ti.com/lit/sg/scyt129g/scyt129g.pdf[3]          Nexperia Selection Guide_2023. Nexperia B.V., 2023.
https://assets.nexperia.com/documents/selection-guide/Nexperia_Selection_guide_2023.pdf[4]          Logic Application Handbook. Product Features and Application Insights. Design Engineer’s Guide. Nexperia B.V., 2021.
https://assets.nexperia.cn/documents/brochure/Nexperia_LOGIC_Handbook_201029.pdf[5]          Logic Selection Guide. Fairchild Semiconductor International, 2003.
https://www.mouser.com/catalog/supplier/library/pdf/fairchildlogic.pdf[6]          AVC Advanced Very-Low-Voltage CMOS Logic Data Book. SCED008C. Texas Instruments, 2003. https://www.ti.com/jp/lit/ug/sced008c/sced008c.pdf

Flyers, leaflets, product briefs, selection guides:
[7]          Our extensive package range provides maximum flexibility. Nexperia B.V., n. d.
https://assets.nexperia.cn/documents/leaflet/Nexperia_package_poster.pdf[8]          Save more space with combination logic. Nexperia B.V., n. d.
https://assets.nexperia.com/documents/leaflet/Nexperia_document_Logic_CombinationLogic_infocard_201710.pdf[9]          Single configurable logic. Nexperia B.V., n. d.
https://assets.nexperia.com/documents/leaflet/Nexperia_document_leaflet_Logic_SingleConfigurableLogic_201812.pdf[10]        Mini Logic – MicroPak portfolio. Nexperia B.V., 2018.
https://assets.nexperia.com/documents/brochure/Nexperia_document_guide_MiniLogic_MicroPak_201808.pdf[11]        Mini Logic – PicoGate portfolio. Nexperia B.V., 2019.
https://assets.nexperia.cn/documents/brochure/Nexperia_document_guide_MiniLogic_PicoGate_201901.pdf[12]        NXP’s Mini Logic portfolio. NXP. B.V., 2015.
https://www.nxp.com/files-static/nxp/white_paper/Mini-Logic-whitepaper.pdf[13]        Advanced ultra-low power CMOS logic for battey-powered systems. Nexperia B.V., 2019.
https://www.paltek.co.jp/dcms_media/other/Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904.pdf[14]        Automotive-qualified logic in space-saving microPak packages. Nexperia B.V., 2019.
https://assets.nexperia.com/documents/leaflet/Nexperia_document_leaflet_Logic_Automotive_MicroPak_solutions_201904.pdf[15]        TinyLogic. Fairchild’s Offering. Fairchild Semiconductor, 2007.
https://pdf.directindustry.com/pdf/fairchild-semiconductor/tinylogic-product-overview/33535-441097.html

https://web.pa.msu.edu/hep/atlas/l1calo/hub/hardware/components/other_ic_and_semiconductors/Not_Cuurently_Used_In_Hub_Design/fairchild_selector_guide_TinyLogic.pdf

Application notes:
[16]        Maier, Emrys: It’s all in the family: a brief guide to logic family selection. TI E2E design support forum, September 10, 2015.
https://e2e.ti.com/blogs_/b/analogwire/posts/it-s-all-in-the-family-a-brief-guide-to-logic-family-selection[17]        Logic data sheet parameters. Application note AN11733. Nexperia B.V., 2019.
https://assets.nexperia.cn/documents/application-note/AN11733.pdf[18]        Lin, Samuel: How to Select Little Logic. Application Report SCYA049A.  Texas Instruments, 2016.
https://www.ti.com/lit/an/scya049a/scya049a.pdf[19]        Maxwell, Chris; Nana, Tomido: Application of the Texas Instruments AUC Sub-1-V Little Logic Devices. Application Report SCEA027A. Texas Instruments, 2002.
https://www.ti.com/lit/an/scea027a/scea027a.pdf[20]        Cockrill, Chris; Cohee, Shawn; Nana, Tomido: Texas Instruments  Little Logic Application Report. Application Report SCEA029.  Texas Instruments, 2002.
https://www.ti.com/lit/an/scea029/scea029.pdf[21]        Understanding Schmitt Triggers. Application Brief SCEA046a. Texas Instruments, 2022.
https://www.ti.com/lit/an/scea046a/scea046a.pdf[22]        Benefits and Issues on Migration of 5-V and 3.3-V Logic to Lower-Voltage Supplies. Application Note SDAA011A. Texas Instruments, 1999.
https://www.ti.com/lit/an/sdaa011a/sdaa011a.pdf[23]        Portability and Ultra Low Power TinyLogic. Application Note AN-5055. Fairchild semicoductor/onSemi, 2004.
https://www.onsemi.com/download/application-notes/pdf/an-5055cn.pdf[24]        Zlotnick, Fred; Diaz, Jess: Unique and Novel Uses for ON Semiconductor’s New One-Gate Family. AND8018/D. ON Semiconductor, 2000.
https://www.onsemi.com/pub/Collateral/AND8018-D.PDF

Data sheets (1): buffers, inverters, and gates
Data sheets can be easily found by visiting the manufacturer’s websites (see below in the Sources section) and making good use of the search functions.

Data sheets (2): configurable gates
Here we mention the most widespread devices and refer to different logic families to show examples of voltage ranges, packages, and so on.[25]        TinyLogic ULP-A Universal Configurable Logic Gates NC7SV57, NC7SV58. Data Sheet. Semiconductor Components Industries, LLC, 2019.
https://www.onsemi.com/pdf/datasheet/nc7sv58-d.pdf[26]        74AUP1G57 Low-power configurable multiple function gate. Product data sheet. Nexperia B.V., 2022.
https://assets.nexperia.com/documents/data-sheet/74AUP1G57.pdf[27]        74LVC1G58 Low-power configurable multiple function gate. Product data sheet. Nexperia B.V., 2022.
https://assets.nexperia.com/documents/data-sheet/74LVC1G58.pdf[28]        74LVC1G97 Low-power configurable multiple function gate. Product data sheet. Nexperia B.V., 2022.
https://assets.nexperia.com/documents/data-sheet/74LVC1G97.pdf[29]        74AUP1G98 Low-power configurable multiple function gate. Product data sheet. Nexperia B.V., 2022.
https://assets.nexperia.com/documents/data-sheet/74AUP1G98.pdf[30]        74LVC1G99. Ultra-configurable multiple function gate; 3-state. Product data sheet. Nexperia B.V., 2019.
https://assets.nexperia.com/documents/data-sheet/74LVC1G99.pdf

Data sheets (3): special devices
[31]        SN74LVC1G0832  Single 3-Input Positive AND-OR Gate. Data sheet SCES606D. Texas Instruments, 2013.
https://www.ti.com/lit/ds/sces606d/sces606d.pdf[32]        SN74LVC1G3208 Single 3-Input Positive OR-AND Gate. Data sheet SCES605B. Texas Instruments, 2013.
https://www.ti.com/lit/ds/sces605b/sces605b.pdf[33]        Small Signal Schottky Diodes. Seelctor Guide, Vishay Intertechnology,Inc.; n. d.
https://www.vishay.com/docs/49470/sg_small.pdf[34]        BAT54, BAT54A, BAT54C, BAT54S Small Signal Schottky Diodes, Single and Dual.
Vishay Intertechnology,Inc.; 2023.
https://www.vishay.com/docs/85508/bat54.pdf[35]        SN74F1056 8-Bit Schottky Barrier Diode Bus-Termination Array. Data sheet SDFS085A. Texas Instruments, 1997.
https://www.ti.com/lit/ds/symlink/sn74f1056.pdf[36]        NX3L4051 Single low-ohmic 8-channel analog switch. Product data sheet. NXP Semiconductors, 2020.
https://www.nxp.com/docs/en/data-sheet/NX3L4051.pdf

Voltage level translation:
[37]        Matthes, Wolfgang: Solving Level-Translation an Logic Problems: Using Discrete Components. Bonus Digital Edition Feature Addition, Circuit Cellar, Issue 395, June 2023.[38]        Lacoste, Robert: Voltage-Level Translation Techniques. Managing Mixed-Voltages. Circuit Cellar, Issue 365, December 2020, p. 68-74.[39]        Voltage Level Translation Guide 2014. scb018h. Texas Instruments, 2014.
https://www.ti.com/lit/ml/scyb018h/scyb018h.pdf[40]        Logic Translator Guide. Nexperia B.V., 2021.
https://assets.nexperia.com/documents/brochure/Nexperia_document_guide_Logic_translators.pdf[41]        SN74AUP1T97 Single-Supply Voltage-level Translator with Nine Configurable Gate Logic Functions. Data Sheet SCES613J. Texas Instruments, 2020.
https://www.ti.com/lit/ds/symlink/sn74aup1g97.pdf[42]        SN74AUP1T98 Single-Supply Voltage-level Translator with Nine Configurable Gate Logic Functions. Data Sheet SCES614I. Texas Instruments, 2013.
https://www.ti.com/lit/ds/symlink/sn74aup1t98.pdf[43]        McCaughey, Mac; Maier, Emrys; Spurlin, Craig: Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards. Application Report SCEA030B. Texas Instruments, 2015.

https://www.ti.com.cn/cn/lit/an/scea030b/scea030b.pdf[44]        Dhond, Prasad: Selecting the Right Level-Translation Solution. Application Report. Texas Instruments, 2004.
https://www.ti.com/lit/an/scea035a/scea035a.pdf[45]        Cockrill, Chris; Land, Ryan; Maier, Emrys: LVxT Family of Single Supply Translating Logic Gates. Application Note SCEA047B.  Texas Instruments, 2022.
https://www.ti.com/lit/an/scea047b/scea047b.pd

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How to use CPLDs to integrate glue logic and other gate-level logic functions:
[46]        Steele, Denny: Cut Power 100X Using CPLD Coprocessors in Portable Applications. Altera, 2007.[47]        Six Ways to Replace a Microcontroller  with a CPLD. White Paper WP-01041. Altera, 2007.[48]        Using Zero-Power CPLDs to Substantially Lower Power Consumption in Portable Applications.  White Paper WP-01042. Altera, 2007.

Implementing logic functions by microcontrollers:
[49]        The PACE Microprocessor. A Logic Designer’s Guide to Program Equivalents of TTL Functions. National Semicondcutor Corporation, 1976.
https://archive.org/details/bitsavers_nationalpaMar76_7788173
http://bitsavers.trailing-edge.com/components/national/pace/4200127X_logDesTTLMar76.pdf[50]        Frenzel, Lou: Replace Fixed-Function IC with Low-Cost Microcontrollers. Electronic Design, May 29, 2018. https://www.electronicdesign.com/technologies/analog/article/21806564/replace-fixedfunction-ics-with-lowcost-microcontrollers[51]        Mitra, Sumit: PLD Replacement. Application Note AN511. Microchip Technology, Inc. 1997.
https://ww1.microchip.com/downloads/en/Appnotes/00511e.pdf

A previous version:
http://bitsavers.trailing-edge.com/components/microchipTechnology/_dataBooks/1993_Microchip_Embedded_Control_Handbook.pdf (on pages 2-59 to 2-78).

A few examples of vintage literature concerning the basics of digital design:
[52]        Morris, Robert L.; Miller, John R. (ed.s): Designing with TTL Integrated Circuits. Texas Instruments/McGraw-Hill, 1971. http://www.bitsavers.org/pdf/ti/_Texas_Instruments_Electronics_Series/Morris_Designing_With_TTL_Integrated_Circuits_1971.pdf[53]        What a Designer Should Know. Application Report EB192E. Texas Instruments, 1995.[54]        Design Considerations for Logic Products. Application Book SDYAE01. Texas Instruments, 1998.[55]        Implications of Slow or Floating CMOS Inputs. Application Report SCBA004C. Texas Instruments, 1998.[56]        Overview of IEEE Standard 91-1984. Explanation of Logic Symbols. Application Report SDYZ001A. Texas Instruments, 1997.[57]        Nolan, Stephen M.; Soltero, Jose M.; Rao, Shreyas: Understanding and Interpreting Standard-Logic Data Sheets. ApplicationReport SZZA036C. Texas Instruments, 2016. https://www.ti.com/lit/an/szza036c/szza036c.pdf[58]        Haseloff, Eilhard: Live Insertion. Application Report SDYA012. Texas Instruments, 1996. https://www.ti.com/lit/an/sdya012/sdya012.pdf[59]        Haseloff, Eilhard: Designing with Logic. Application Report SDYA009C. Texas Instruments, 1997. https://www.ti.com/lit/an/sdya009c/sdya009c.pdf

SOURCES
The author’s project homepages:
https://www.realcomputerprojects.dev
https://www.controllersandpcs.de/projects.htm

Standards:
https://www.jedec.org/

https://www.jedec.org/standards-documents
JECEC committees related to our topic:
JC-11: Mechanical standardization
JC-40: Digital Logic
JC-16: Interface Technology. The committee is als resposible for the voltage level specifications. The basic standard is JESD8.
JESD8C: 2.7 V to 3.6 V
JESD8-5: 2.3 V to 2.7 V
JESD8-7: 1.65 V to 1.95 V
JESD8-11: 0.9 V to 1.65 V
JESD8-12: 0.8 V to 1.3 V

Free vintage literature:
https://archive.org/details/folkscanomy_electronics
http://www.bitsavers.org/pdf/
http://www.bitsavers.org/components/
http://bitsavers.trailing-edge.com/pdf/

Some links to manufacturers:
https://www.ti.com
https://www.nexperia.com
https://www.onsemi.com
https://www.nxp.com
https://www.toshiba.com
https://www.st.com

A few more specific links:
https://www.ti.com/logic-voltage-translation/overview.html
https://www.ti.com/logic-voltage-translation/logic-gates/products.html
https://www.nexperia.com/products/analog-logic-ics
https://www.onsemi.com/products/timing-logic-memory/standard-logic
https://www.nxp.com/products/peripherals-and-logic:PERIPHERALS-AND-LOGIC
https://www.st.com/en/automotive-logic-ics/gates.html
https://www.ti.com/logic-voltage-translation/specialty-logic-ics/bus-termination-arrays/products.html
https://www.nexperia.com/products/diodes/schottky-diodes-and-rectifiers/schottky-diodes-and-rectifiers-if-lt-1-a/
https://www.ti.com/logic-voltage-translation/specialty-logic-ics/bus-termination-arrays/products.html

RESOURCES
Nexperia | www.nexperia.com
NXP Semiconductors | www.nxp.com
Onsemi | www.onsemi.com
STMicroelectronics | www.st.com
Texas Instruments | www.ti.com
Toshiba | www.toshiba.com

PUBLISHED IN CIRCUIT CELLAR MAGAZINE • NOVEMBER 2023 #400 – Get a PDF of the issue

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Wolfgang Matthes has developed peripheral subsystems for mainframe computers and conducted research related to special-purpose and universal computer architectures for more than 20 years. He has also taught Microcontroller Design, Computer Architecture and Electronics (both digital and analog) at the University of Applied Sciences in Dortmund, Germany, since 1992. Wolfgang’s research interests include advanced computer architecture and embedded systems design. He has filed over 50 patent applications and written seven books. (www.realcomputerprojects.dev and
www.controllersandpcs.de/projects).

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Designing Combinational Circuitry

by Wolfgang Matthes time to read: 34 min