Controlled Impedance Routing
Robert wraps up his article series on how to properly design printed circuit boards. Here in Part 3, he looks at how to handle PCB trace impedance, and shares techniques for dealing with high-speed digital signals.
Welcome to “The Darker Side.” This article is the third and last of my series on printed circuit boards (PCBs). In the previous columns, I explained how to design and route multilayer boards, such as ubiquitous 4-layer PCBs. I also introduced more complex topics, including blind and buried vias, since you may encounter them in dense circuits. This month, I will conclude with controlled impedance—why and when you should care about PCB trace impedance. I will also briefly show techniques used for high-speed digital signals such as differential pairs. As usual, I will stay as application-oriented as possible, so don’t be afraid, and enjoy!
Impedance matching is one of my favorite topics, probably because I am working 80% of my time on RF designs. Nevertheless, it is also a concern for plenty of non-RF designs, in particular, when using fast digital signals. Simply speaking, even your small Raspberry Pi will probably not work without proper routing of its memory and I/O signals. Since USB and gigabit-Ethernet are replacing slow RS-232 interfaces, knowing some basics on impedance matching is now a must for every designer.
During the past 15 years, I have devoted several columns to this subject, so I will not burden you with another long explanation on impedance matching. Briefly, whenever you need to connect a source to a load and want to transfer as much power as possible from source to load, then you must take care of impedance matching. As a refresher, take a look at Figure 1a, which shows the easy case of DC. Here I assumed that the source is a battery. Since nothing is perfect, this battery has an internal parasitic serial resistance RSRC. If you connect a load resistor RLOAD, then power will be transferred to the resistor and heat will be generated. This power will be maximum when RSRC = RLOAD. That’s impedance matching in a nutshell. If you have any doubt, do the calculation or read one of my old columns (for example: “The Darker Side – Impedance matching, again…,” Circuit Cellar 319, February 2017 ).
In the case of AC signals (Figure 1b, this is exactly the same, but resistances (R) must be replaced by impedances (Z). Impedances have both a resistive (R) and a reactive (X) part, the latter being either inductive (positive) or capacitive (negative). As in the case of DC, the power transfer will be maximum when source and load impedances are matched. In AC, the match will be perfect if the source and load resistances are equal, and when reactances are equal but with opposite signs. A capacitive source must be matched with an inductive load, and vice-versa. The other difference between DC and AC is that in the latter, the impedances are usually frequency dependent, which makes life a bit more challenging—but you got the idea.
Let’s imagine that you are working on a wireless design. Your PCB includes a transmitter/receiver module (your choice: Wi-Fi, Bluetooth, LoRa or anything else) connected to an antenna. You scratch your head, trying to decide how to route this connection on the PCB. Because my topic is PCB traces and not sources and loads, I will assume that the module antenna port and the antenna are impedance matched, which usually means that they both have a standardized 50Ω resistive impedance. Now, to keep a good matching, the PCB trace interconnecting these two devices will also need to have a so-called “characteristic impedance” of 50Ω.
What is this characteristic impedance about? How can a trace have an impedance? This notion is linked to the transmission line theory. I think it is easier to first explain it using the example of a coaxial cable (Figure 2). Imagine that you have a piece of coaxial cable, and that you divide it into several very small sections, each of length dl. Each section has a small internal wire, which could be modeled as a small serial inductance. Because the internal wire is also capacitively coupled to the braid shield, the model must also include a small capacitor between the wire and the ground.
The parasitic inductance and capacitance are roughly proportional to the length of the small section, and so can be noted L.dl and C.dl, with L and C respectively in Henries per meter and farads per meter. If we apply a voltage on one end of the cable, then some current will flow until all capacitors are charged. If the cable has an infinite length (I know, this is difficult to buy…) then this current will flow forever, giving the equivalent of an actual stable impedance. This impedance is called the characteristic impedance of the cable, and is, in fact, simply the square root of L over C.
So, the characteristic impedance of a transmission line is its actual impedance, if its length were infinite. Now, what happens if you use a finite length of such a transmission line? The behavior is illustrated in Figure 3, and I always find it quite fun. An infinite roll of cable with 50Ω characteristic impedance will have an impedance of 50Ω, so it will be perfectly matched with a 50Ω source. I illustrated this situation on the top part of Figure 3. What happens if you split the cable into two sections, starting with a finite length section (middle example in Figure 3)? In Figure 3, the middle section, on the right, will still have an infinite length, so its impedance will still be 50Ω (an infinite minus a finite length, that’s still infinite). Therefore, the right section with infinite length could be replaced by its equivalent—50Ω resistor, or any other load with a 50Ω impedance (bottom illustration).
Check again what we have done. This short example shows you that a transmission line with a given characteristic impedance Z doesn’t change the impedance of a load with the same impedance Z. That’s why you should always use a cable or trace with a proper characteristic impedance when impedance matching is a concern. And this is the case whenever power transfer needs to be optimized.
Ok, now what happens if, instead of a coaxial cable, you simply have a copper trace on a side of a PCB, with a ground plane below it? Such a structure is called a “microstrip.” Exactly as with the example of a coaxial cable, the trace can be modeled as small sections, each with a serial inductor and parallel capacitor (Figure 4). This trace will also have a given characteristic impedance. What are the parameters that will influence the value of this characteristic impedance?
The first—and most easily managed by the designer—is the trace width. If you increase the trace width, then the trace inductance will be reduced. Simultaneously, the trace-to-ground capacitance will increase. Remember that the characteristic impedance is the square root of L over C. Increasing the trace width will then reduce its characteristic impedance.
The second parameter is the thickness of the PCB structure, or more exactly, the distance between the microstrip trace and the ground plane (which could be either on the bottom side of the PCB or on one of its internal layers). Reducing this thickness will increase the capacitance between the trace and the ground plane, so it will also reduce the characteristic impedance of the line.
The third parameter is the material used to manufacture the PCB—more specifically, its so-called “dielectric constant.” For a given thickness, increasing the dielectric constant will also reduce the characteristic impedance. Typical PCBs are built using a standard FR4 substrate, which has a dielectric constant not precisely defined but around 4.6. You can also select high-end substrates dedicated to sensitive RF or high-speed circuits. These have very precise dielectric constants, ranging from 3 to more than 10, depending on the designer’s needs. Such substrates also have considerably lower losses. But that’s a whole other topic.
Let’s stay on impedances and summarize. If you want to connect a 50Ω source to a 50Ω load on a PCB with proper impedance matching, you should design a PCB trace with a characteristic impedance as close to 50Ω as possible. With a given PCB structure, there should be a given trace width for that. Characteristic impedance will be reduced with wider traces, a thinner PCB or higher dielectric constant, and will, of course, be increased with thinner traces, a thicker PCB or lower dielectric constant.
The Web is full of tools to help you to calculate such a microstrip. For the purpose of this article, I downloaded a nice Windows application, provided free of charge by Saturn PCB Design . See Figure 5 for a calculation of a 50Ω microstrip trace. Here I assumed that the PCB was a standard FR4 with a thickness of 0.8mm. The tool also lets you select copper and plating thickness, which slightly influence the trace characteristic impedance. With such a setup, a trace width of 1.5mm provides a calculated characteristic impedance of 49.9Ω. By the way, don’t be frightened by the 0.1Ω error. In typical designs, a characteristic impedance error of even 1Ω or 2Ω will not have any measurable impact. This is dependent on the signal frequency and trace length, but 49.9Ω is clearly good enough here.
With all that in mind, you may simply use a trace with a width of 1.5mm on such a 0.8mm thick PCB, and route it from the wireless module to the antenna. Easy, isn’t it? Well, in real life, such a calculated microstrip trace width is often too large. Designs today are full of fine-pitch components, and a 1.5mm trace simply will not be usable on them, or will use too much board space. Moreover, I took the example of a 0.8mm-thick PCB. If I did the calculation with a more standard 1.6mm PCB, then the trace width would be 3mm—huge! You must also keep in mind that a microstrip shouldn’t have any other trace too close to it, so this further increases the use of board space.
REDUCED TRACE WIDTH
So, how to reduce the trace width while keeping a 50Ω characteristic impedance on a PCB? Reducing the trace width will increase the impedance, so we should find counter-measures to decrease it. The most common solution? Simply reduce the PCB thickness, or more specifically, the distance between the top-layer microstrip and the ground plane. This is usually done by using a multilayer PCB, and putting the ground plane on the first internal layer, as close as possible to the top layer. As explained in Part 1 of this series (Circuit Cellar 367, February 2021 ), PCB manufacturers can propose different PCB stack-ups, and specifying a low thickness for the so-called “top prepreg” will help to reduce the trace width. For example, with a thickness of 0.25mm, a trace width of 0.35mm gives 50Ω, far easier to use. You could also select a substrate with a higher dielectric constant than FR4, but this costs more.
Another solution is to move from a simple microstrip to a more complex transmission line structure, such as the co-planar waveguide illustrated in Figure 6. A complicated expression for a quite simple thing. An extra ground plane is simply added on the top layer, with a precisely defined distance G to the signal traces. This ground can then be designed to be quite close to the trace, say 0.2mm away. That increases the parallel capacitance which reduces the impedance and allows you to have thinner traces. The only precaution is that the top layer ground plane actually should be a ground as good as the inner layer full ground plane. This means that plenty of ground vias should interconnect these two ground planes, and the higher the frequency, the closer the vias.
One more example is the stripline structure (Figure 7). Here the signal trace is sandwiched between two ground planes. Once again, the trace width could be thinner, because the capacitance is doubled. Such a structure also provides a better shielding.
Until now, I used wireless projects as examples, because impedance matching is necessary to improve the performance of such a system. Power losses mean reduced communication range, and everyone wants to have a higher range. There is, however, another area where impedance matching is a key concern: fast digital transmissions. I devoted a column to this topic so don’t hesitate to read it again (“The Darker Side – Digital Line Terminations,” Circuit Cellar 309, April 2016 ). High speed digital systems have fast signal transitions, which implies very high frequency harmonics. In such systems, improper impedance matching means signal reflection back and forth on the lines, which leads to corrupted signal transitions and system errors. Moreover, such high-speed digital systems typically use several parallel lines, which must be not only impedance matched but also length matched, to enable the bits to arrive at their destination at the same time.
One basic and common structure used in digital systems is differential lines, where the information is sent through two traces with opposite polarities. What are some examples of communication protocols using differential lines? Well, nothing less than Ethernet, USB, PCI express, HDMI, display port, all LVDS-based devices, RS422/RS485, serial-ATA, DDR-RAMs and a couple of others. The odds that you will encounter them are then close to 100%. Differential lines also have a given differential characteristic impedance, which is easily calculated (see Figure 8). It is a function of the line width, line spacing and PCB structure.
As a nice example, I can’t resist the pleasure of showing you a small part of the routing of one of the PCB’s designed recently by my company (Figure 9). You will easily see plenty of differential length-matched pairs. Moreover, this is just a very small part of the complexity. For simplicity, Figure 9 shows only two layers of this 12-layer design, and plenty of other differential pairs are routed on the other layers. My colleague in charge of this design lost some hair in the process.
Here we are. I know that not all of you are designing complex PCBs every day, but understanding the technology and constraints associated with proper signal routing and impedance matching should be in the bag of tricks of every engineer. I know that, once again, I have only scratched the surface of the subject, even if I devoted three columns to this PCB topic. I also could have talked about plating and coating, finishing and lead-free concerns, flex circuits design, PCB loss tangent, glass transition temperature, exotic substrates, milling and V-cut concerns, silkscreen, soldermask, bare-board test and a couple of other subjects. Maybe for future articles? Or maybe you would be interested in writing an article for Circuit Cellar on these topics. Don’t hesitate!
 “Impedance Matching Fundamentals” Circuit Cellar 319, February 2017
 Saturn PCB toolkit https://saturnpcb.com/saturn-pcb-toolkit
 “Understanding Proper PCB Design (Part 1)” Circuit Cellar 367, February 2021
 “Digital line terminations” Circuit Cellar 309, April 2016
Saturn PCB Design | www.saturnpcb.com
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • JUNE 2021 #371 – Get a PDF of the issueSponsor this Article
Robert Lacoste lives in France, between Paris and Versailles. He has more than 30 years of experience in RF systems, analog designs and high-speed electronics. Robert has won prizes in more than 15 international design contests. In 2003 he started a consulting company, ALCIOM, to share his passion for innovative mixed-signal designs. Robert is now an R&D consultant, mentor and trainer. Robert’s bimonthly Darker Side column has been published in Circuit Cellar since 2007. You can reach him at firstname.lastname@example.org.