Making the Chips That Make Electronics Possible
In this second part of his article on silicon chip manufacturing, Faiz delves deeper into the chip fabrication process. He looks at manufacturing processes that are needed to complete and package silicon ICs, and describes some important individual processes in more detail.
Part 1 of this article described the production of silicon wafers, followed by the first steps toward the manufacture of integrated circuits. Those steps, culminating in the fabrication of transistors and their so-called local interconnects, go by the name of front end of line (FEOL) processes. A lot more needs to be done, however, before we have finished and packaged chips. The back end of line (BEOL) processes—the subject of Part 2 of this article—start once the transistors have been fabricated and connected to each other. These processes create the complex circuit patterns that the chip architects designed to realize the desired chip functionality. A wafer contains many IC chips arranged in a 2D array (Figure 1). All chips get processed in parallel as various manufacturing operations are performed on the wafer.
A silicon wafer with IC dies. Courtesy: Lam Research Corporation.
Completing the chips
The world of chip designers is entirely different from that of chip fabricators. The two do not need to interact with each other. Their only connection is through transistor characteristics data that the fabs provide to circuit designers, and the finished circuit designs that the designers provide to the fab in a final step called tape out. The final circuit design is used to create a set of photographic plates, called masks or reticles, which will be used to create the structures on silicon wafers.
Each IC, called a die in the industry, can be thought of as a multilayer, cake-like structure where different materials, in specific patterns, are layered one above the other. The lowest layers are created during FEOL processes, and the layers above are created with BEOL processes. These latter layers, principally, provide circuit interconnections. Modern ICs are so complex, with billions of transistors on each die, that interconnecting them all with one or two layers of wiring is impossible. Anywhere from six to ten wiring layers are needed on advanced digital logic chips.
Each wiring layer is made with patterned copper tracks, typically 10 to 20nm wide. Adjacent wiring planes are vertically separated from each other by a layer of insulating silicon dioxide. Extremely tiny holes, called vias, filled with tungsten metal plugs, are formed at specific locations in the interlayer dielectric to provide electrical connectivity between neighboring wiring layers. The topmost wiring layer is capped by a layer of silicon nitride to protect everything underneath. Electrical bond pads, which will ultimately connect the chip to the outside world, emerge out of this capping layer.
There are a number of standard processes that are repeatedly carried out during wafer processing. The main ones consist of material deposition, creating a patterned plastic (resist) film on top of it, and material etching through openings in this film. Together, these three processes create a patterned material layer, as dictated by the requirements of the circuit design. Most equipment in any fab is dedicated to carrying out these steps. Let’s look at how these processes work.
Material deposition
Semiconductor manufacture requires repeated deposition of materials—some electrically conducting, like metals, others non-conducting, like oxide-based insulators. Most materials are deposited as a layer of uniform thickness across an entire wafer. The process generally used for this purpose is called sputter deposition.
In this process, multiple wafers are loaded inside a stainless-steel chamber (Figure 2), which is then evacuated. A gas, such as argon, is introduced into the chamber at a very low pressure. Using microwave energy, the gas is ionized to form a plasma, consisting of free electrons and positively charged argon ions. A DC voltage is applied between a metal platter that holds the wafers and a “target” disk made of the material to be deposited. The target is made the cathode, whereas the wafers become anodes. Argon ions are attracted toward the target and slam into it with sufficient force to dislodge atoms of the target material. These sputtered atoms then deposit on the wafers lying underneath, forming a smooth uniform film all over the wafers.
Silicon wafers inside a sputter coating chamber. Courtesy: Applied Materials Corporation.
The duration of the sputtering process (among other factors) controls the thickness of the deposited film. Sputtered films are conformal—that is, they conform to the topography found on the wafer surface. Thus, vertical features get covered by the deposited material on all sides. This is important because modern ICs contain 3D structures, such as MOSFET gates and DRAM capacitors.
Sputtering can be used to deposit almost any desired material—even those with high melting points, such as tungsten, because no melting is involved and so high temperatures are not needed. Fabs generally house several sputtering tools dedicated to each particular material to be deposited. This ensures a high wafer throughput, and guards against tool breakdown, to some extent.
Photolithography
Material deposition, described above, is followed by etching to remove material from locations where it is not needed. This leaves the deposited material in specific shapes. These two processes—material deposition and etching—are repeated many times to build the chip, layer by layer. Material deposition is always carried out such that the deposited material covers the entire wafer. This is called blanket deposition. The next step, where deposited material is selectively etched away from specific locations, is preceded by an extremely important intermediate process that defines the pattern in which material will be etched. This patterning process, called photolithography, is the most critical of all semiconductor manufacturing processes. It is the advances in photolithographic patterning technology that advance IC chip manufacturing from one generation to the next by enabling the patterning of ever smaller features.
Conceptually, photolithography is a simple photographic imaging process. After material deposition, a light-sensitive polymer called a photoresist is coated on an entire wafer by spinning it at high speed and dropping the liquid photoresist solution on it. The spinning of the wafer spreads the resist on the wafer as a thin uniform film, which dries to form a photosensitive coating covering the wafer. After a short baking step to remove any residual solvent, the resist-coated wafer is placed in a photolithography machine.
Inside the lithography scanner, as it is called, a pattern is projected on the wafer’s resist coating by shining ultraviolet (UV) light through a mask plate. This image-bearing plate is called a reticle and carries the desired etching pattern as an image. The reticle consists of a quartz plate printed with a chromium metal pattern. Where there is no chromium, UV radiation passes through the plate to strike the wafer, and where there is chromium, UV radiation is blocked and does not reach the wafer. The manufacture of a typical IC might require anywhere from twenty-five to fifty reticles (and as many photolithographic patterning steps).
UV exposure causes photochemical changes in the resist film, causing the resist at locations that received UV exposures to become soluble in a liquid developer. The resist at other locations, which did not get exposed to UV radiation, does not dissolve in the developer. In this way, after exposure and development, a patterned resist film is left on top of the blanket deposited material (Figure 3).
The photolithography process.
The subsequent etch process will use the patterned resist as a stencil to selectively etch the underlying material only where there are openings in the resist film. Other regions remain protected by the resist (hence its name—it resists the action of etchants). After the etch process, the patterned resist layer can be stripped away, leaving the deposited material in the desired 2D pattern on the entire wafer.
As the dimensions of device features on chips have shrunk from hundreds of nanometers to less than 10 nanometers in leading edge devices (advanced memories and processors), it has become difficult to accurately reproduce the reticle image on the wafers. Optical diffraction effects degrade lithographic resolution as image features come closer together. The main way to circumvent this fundamental physical limitation is to reduce the wavelength of exposure radiation. Thus, historically photolithography exposure wavelength has decreased from 365nm (the so-called i-line wavelength) from mercury vapor lamps, to 248nm from krypton fluoride (KrF) excimer lasers, to 193nm from argon fluoride (ArF) excimer lasers. The latest development is the introduction of extreme UV (EUV) wavelength, at 13.5nm. Along with other measures, these changes have enabled manufacturers to produce chips with ever smaller devices, boosting both performance and energy efficiency.
Material etching
The deposition of a material almost always must be followed by an etch step. This ensures that the material is left in only those locations where it is needed, such as for forming contacts to transistors’ source, drain and gate regions, forming metal interconnects according to the desired circuit pattern, and so forth. In the early days of the semiconductor industry, after photolithography was performed to define places from which deposited material was to be removed, the wafer was immersed in a liquid etchant that could dissolve away the material through a chemical reaction. Acids, for example, can etch several metals.
As the devices on ICs steadily shrank in size, wet etching gradually became inadequate. This is because etching with wet chemicals not only removes material in the vertically downward direction but also simultaneously attacks the sides of the region being etched. The lateral material erosion is undesirable because it unintentionally alters the size of on-chip features.
The solution to this processing problem came with the development of dry etching technology, also called plasma etching. A radically different technology from wet etching, dry etching makes use of ionized gases inside a chamber where a wafer to be etched is placed (Figure 4). The ionized gases, also called plasma, interact with the wafer in such a way that the ions effectively bombard the wafer surface (covered by a photolithographically patterned resist layer). Wherever there are openings in the resist layer, the ions remove the material through a synergistic combination of physical ion bombardment and a chemical reaction between the ion and the exposed material. This causes the formation of volatile compounds of the etched material which are removed by the vacuum of the processing chamber.
Lam Research Sense.i dry etch tool. Courtesy: Lam Research Corporation.
Dry etching enables vertical etching without any erosion of the side wall of the feature being etched. This has made this technique universally applicable to the entire wafer fabrication process flow, and dry etching is now the second most important process in the industry after photolithography. Figure 5 shows a commercial dry etch machine. A typical fab will house several dozens of such machines with multiple units dedicated to the etching of particular materials.
Silicon wafer inside a dry etch machine. Courtesy: Lam Research Corporation.
Freeing up the chips
Once a wafer starts on its journey through the fab, it can take several weeks to emerge at the other end as a fully processed and tested wafer. Thousands of individual operations are carried out in succession on the wafer and its progress is carefully monitored during its travels. After every few steps, a defect scan using special inspection and metrology tools is carried out to check for pattern fidelity, particulate contamination, and process-related debris on wafers. If any concerns are flagged, then wafers may be sent for additional washing steps or scrapped altogether. All processing is guided by statistical process control (SPC) charts that show allowable levels of departure from various metrics, such as deposited film thickness, etch depths, and so on.
Finished wafers are sealed and packed in containers ready for dispatch to a separate dicing and packaging facility. Traditionally, these have been in countries where labor is less expensive, such as Malaysia, the Philippines, and Thailand. The companies carrying out this work are either standalone operations or captive entities of major semiconductor manufacturers.
Here, the wafers are first probed to test each die for functional metrics, while all the dies are still on the wafer. Large, automated wafer testers are used for this purpose. These machines make a multiprobe head descend on each die in turn. The probe pins make contact with exposed bond pads on the chips. Through these pins, power and signals are injected and monitored to check various functional parameters. Many tests are performed in quick succession to thoroughly verify all operational metrics. Any non-functional dies found at this stage are clearly marked and will be discarded later.
After on-wafer die testing, the wafers go through a singulation process where a precision diamond saw, or laser scribe, is used to cut through the wafer and release individual dies. The good ones will be packaged in appropriate chip packages. The number of working dies obtained, as a fraction of all dies on a wafer, is the yield of the process and is one of the most important metrics for semiconductor manufacturing. When a particular manufacturing process is developed, its yield is usually low initially (approximately 25 to 40%). As the process matures through more manufacturing experience and tweaks, the yield gradually rises. A yield of 90% or higher is considered excellent, and is the mark fabs strive for. For complex, state-of-the-art devices, it may be impossible to raise the chip yield beyond 80%; in these cases that is considered acceptable because of the high prices such ICs can be sold at. It is not difficult to see that yield management is a serious business in any fab because of its direct impact on profitability.
Dies, once freed from the confines of their wafers, need to be packaged for end use. Different kinds of uses may require different types of packages. Thus, several different types of packages can be used for the same kind of die. These are called packaging variants. The chips are molded with resin on a metal die frame to securely encapsulate them. In other cases, ball grid array packages may be used. Higher power dissipation devices are usually packaged in ceramic rather than plastic packages for better heat transfer. With the advent of system-on-chip (SoC) devices and highly advanced memories and processors, chip packaging has become an art in itself.
Packaged devices are finally packed in boxes or on sprocket tapes for use in pick-and-place machines on PCB assembly lines. Products are shipped directly from the packaging facility to industrial consumers and electronic component distributors. Because chip packaging is the last of the major manufacturing operations, by convention devices get printed by that country’s name as the place in which the device was manufactured.
As we’ve seen in this article, semiconductor IC manufacturing is a complex undertaking. Given that the manufacturing equipment is also expensive, with each major tool costing several million to tens of millions of dollars, it is no surprise that there are only a few manufacturers of state-of-the-art chips in the world. With the passage of time, the complexity and costs will only grow further. For those in this business, however, these challenges will open the doors to new opportunities in the years to come. 
In this second part of his article on silicon chip manufacturing, Faiz delves deeper into the chip fabrication process. He looks at manufacturing processes that are needed to complete and package silicon ICs, and describes some important individual processes in more detail.
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • APRIL 2024 #405 – Get a PDF of the issue
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About the author
Faiz Rahman, PhD, is a materials and device engineer, working on novel materials and device structures for both electronics and photonics. He develops new LEDs and solid-state lighting concepts at Electrospell and is also a visiting professor in Electrical Engineering at Ohio University. Faiz is a senior member of the Optical Society of America and of IEEE. His current research interests include the development of nano LEDs, plasmonic structures, and advanced nanofabrication technologies.
