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Digital Line Terminations

Written by Robert Lacoste
Electrical reflections create problems for RF engineers when there is an impedance mismatch between a source and a load. The result can be distortions that jeopardize high-speed transmissions. Robert tackles the subject with an explanation of digital line terminations. Topics Discussed How deal with impedance mismatchesHow to understand digital line terminationsA case exampleHow to prevent electrical reflections Tech Used AppCad from Avago TechnologyLibreOffice Calc from LibreOfficeWavemaster 813zi Oscilloscope from Teledyne Lecroy Welcome back to the Darker Side. In my April 2009 article, "Time Domain Reflectometry," I talked about signal reflections in transmission lines (Circuit Cellar 225). Basically, electrical reflections occur wherever there is an impedance mismatch between a source and a load. This nasty phenomenon is well known to radio frequency engineers who are careful to optimize impedance matching in order to reduce power losses. This is also a concern for digital engineers because signal reflections cause interference in fast digital transmissions, which is a concern as digital clock speeds are increasingly crazy. A PC motherboard simply won't work without the proper management of signal reflections. How are they managing reflections? Well, have you ever seen small resistors on clock and data signals? Do you want to know how to use them—and, more importantly, how to size them? If so, keep reading. This month I will explain digital line terminations and describe some interesting experiments. THE PROBLEMA very simple circuit is enough to explain where the problem comes from. Let's suppose that you have two logic gates chained together—for example, two buffers (see Figure 1a). A logic pulse is applied on the input of the first gate. You expect to get the same pulse on the output of the second one with a little propagation delay. Now let's see how things are actually working (see Figure 1b). The output of the first gate
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Digital Line Terminations

by Circuit Cellar Staff time to read: 13 min