Electrical reflections create problems for RF engineers when there is an impedance mismatch between a source and a load. The result can be distortions that jeopardize high-speed transmissions. Robert tackles the subject with an explanation of digital line terminations.
Welcome back to the Darker Side. In my April 2009 article, “Time Domain Reflectometry,” I talked about signal reflections in transmission lines (Circuit Cellar 225). Basically, electrical reflections occur wherever there is an impedance mismatch between a source and a load. This nasty phenomenon is well known to radio frequency engineers who are careful to optimize impedance matching in order to reduce power losses. This is also a concern for digital engineers because signal reflections cause interference in fast digital transmissions, which is a concern as digital clock speeds are increasingly crazy. A PC motherboard simply won’t work without the proper management of signal reflections. How are they managing reflections? Well, have you ever seen small resistors on clock and data signals? Do you want to know how to use them—and, more importantly, how to size them? If so, keep reading. This month I will explain digital line terminations and describe some interesting experiments.
A very simple circuit is enough to explain where the problem comes from. Let’s suppose that you have two logic gates chained together—for example, two buffers (see Figure 1a). A logic pulse is applied on the input of the first gate. You expect to get the same pulse on the output of the second one with a little propagation delay. Now let’s see how things are actually working (see Figure 1b). The output of the first gate is internally made with transistors, either bipolar or CMOS. Trust me, these transistors are not perfect. This implies that the output impedance of the gate will not be zero as it should with perfect transistors, but maybe some tens of ohms. Let’s call this output impedance Zs. (The “s” is for source, assuming for simplicity that this impedance is the same for a logic 0 and for a logic 1, which is usually not the case.)
Similarly the input of the second logic gate will have a given input impedance, noted Zi. As the bias current of a logic gate is low, this input impedance will usually be high, maybe some hundreds of kilohms.
Lastly, the wire or printed circuit board (PCB) track between the two gates is not a perfect wire either. As illustrated in Figure 1b, each portion of the wire is more or less a small series inductor (the wire itself), with a small parallel capacitor to ground (the capacitance between the wire and the ground). And such a chain of small LC network makes a transmission line, which will have a given characteristic impedance that I will name Zline. This characteristic impedance may be fuzzy if you don’t take any precaution when drawing your PCB, or it could be a well defined value like 50 Ω if you use controlled impedance techniques (R. Lacoste, “Microstrip Techniques,” Circuit Cellar 223, 2009).
Now what actually happen with such a circuit when there is a transition on the input signal?
A SIMPLE CASE
Let’s start by assuming that both the impedance Zs of the source and the characteristic impedance of the line Zline are 50 Ω, but that the load is an open circuit (see Figure 2). This is close to what actually happens if you don’t take any specific care in your design, as the input impedance of a logic gate is far higher that its output impedance.
Now, assume that the input signal is initially at 0 V and then rises quickly to VCC. What will be the respective voltage waveforms on the output of the first gate (VSOURCE) and on the input of the second gate (VLOAD)? Of course, if you assume that everything is fast enough, then both voltages will jump from 0 to VCC and the output of the second gate will be a logic 1, but what happen during the first nanoseconds ?
Remember that neither electricity nor information can propagate instantly. Firstly, the first gate will have a given transmission delay. Then, when the signal will appear at its output, the electrons have no way to know instantly that the other end of the transmission line is an open circuit. Therefore, the voltage at the output of the first gate must initially be identical to the voltage that will be present if the line was infinite. And what is the impedance of such an infinite line of characteristic impedance 50 Ω? 50 ohm of course, that’s the definition of characteristic impedance. But, wait, the first gate has an output impedance of 50 Ω, and is connected to a load that looks like 50 Ω, so the voltage VSOURCE on its output must be VCC/2 and not VCC! And it is actually VCC/2, at least for some nanoseconds as illustrated on Figure 2. Sometime later, depending of the length of the transmission line, this voltage VCC/2 has propagated through the line and appears at the over end. As this other end is open-circuited, the signal will be reflected back to the source. What will be the voltage at that point? Imagine a wave reflected by a wall, the water height will be twice higher than the incident wave as the reflection will add on top of the signal propagating forward. So this will gives a voltage of 2 × (VCC/2) = VCC as expected for a line driven by a logic gate and open-ended. This relected signal will then propagate backward to the source, and, two propagation times later, the voltage on at the output of the first gate will jump from VCC/2 to VCC too. The resulting waveforms at both ends of the wires will then be close to the one illustrated on Figure 2. If you don’t trust me, then just wait a few minutes and I will show you some actual measurements.
In the simple situation I have described above, the source and the transmission line are impedance-matched, so there is only one reflection at the far end. Now imagine a more complex situation were all impedances are different. For example, what will happen if the source impedance Zs is 20 Ω, the line characteristic impedance is 50 Ω and the load impedance is infinite (open circuit)? There will be an initial wave propagating through the wire as before, even if its voltage will be different, and this wave will still be reflected back by the load. But now, as the line and the source are not impedance matched, a part of this reflected signal will be reflected again by the source, giving a new forward signal that will add up on the line voltage! These back and forth reflections will continue forever, with decreasing amplitudes.
So what will be the actual voltage waveforms on both ends of the transmission line? For simplicity, I will assume that the logic gates are fast enough, meaning that the signal propagation time through the transmission line is significantly longer than the slew rate of the signal. In that situation, the waveforms measured on each end of the line are changing value at discrete time steps, giving staircases with varying step amplitudes. The duration of each step is simply twice the propagation time through the line.
How to calculate such signals? There are some high-end simulators dedicated to this kind of problems, but a simple spreadsheet may be enough to understand what’s going on. If we assume that all devices are linear, then there is a simple calculation method named Lattice Diagram (or bounce diagram). The idea is to calculate each reflection and to sum them all. I built such a model using the Libreoffice Calc spreadsheet, and the result is shown in Figure 3. The arrows illustrate the successive back and forth reflections and their corresponding voltages. The plots on the right gives the resulting voltages on the source and load ends of the line, as if they will be measured with an oscilloscope.
At this point, I strongly encourage you to stop reading this article. Download the spreadsheet file from the Circuit Cellar article code and files webpage, download libreoffice (it’s free), and modify the input data (impedances, etc.). Do you see how the resulting waveforms are impacted? Do you see that the higher the impedance mismatch, the higher the problem? Do you see that the waveform shapes are drastically different if the load has a higher or lower impedance than the line? Playing with such a simple model is an invaluable experience.
FIGHTING AGAINST REFLECTIONS
I’m sure that you have understood that such signal reflections introduce distortions that could jeopardize high-speed transmissions. Some 1s could be understood as 0s and vice versa. Now how to minimize these reflections? With better impedance matching, of course. There are basically three solutions. The first idea is to make sure that the load is matched with the transmission line. If there isn’t any reflection on the load side, then there is no problem. Assuming that the input impedance, ZL, of the receiver gate is very high, then you could simply add a resistor between the receiver gate input and the ground, with a value equal to the characteristic impedance ZLINE of the transmission line (see Figure 4a).
This solution provides very clean signals but has one drawback. The power dissipated in the load resistor may not be neglected, especially if the line stays at a level 1 for a long time. A better solution consists of adding a DC-blocking capacitor in series with the load resistor (see Figure 4b). The resistor is still doing its job for high-frequency signals, whereas the capacitor stops any DC current. Theoretically, this is a great solution, but capacitors use board space and may introduce nasty spurious resonances.
The most common solution is simple but a little more difficult to understand (see Figure 4c). Here a series resistor is added on the transmission line, but on the source side. For a 50-Ω transmission line, its value is not 50 Ω but a little less, maybe 22 or 33 Ω. The idea is that this added resistor, added to the output impedance of the source gate, results in a 50-Ω impedance. This will bring us back to the “simple example” presented in Figure 2. If the source and the load are not matched, then the load will reflect some signals. However, this reflection will be stopped after one forward and backward travel through the line as the line and the software are impedance-matched. However, such a series resistor configuration must be used with great care. Why? Look back at Figure 2. The signal on the receiver end is theoretically perfect, but the signal on the source side is very distorted. This is usually not a problem, but it could be if you have a daisy-chained structure. Some nodes will get a clean signal, but not others. Those who have played with RS-485 or CAN networks may remind that parallel load resistors are mandatory at both ends of the line. That’s because series resistors will simply not work on a multipoint topology.
Now it’s time for a small experiment. In order to demonstrate these phenomena, I built a small test board with two fast logic gates connected together. I selected a pair of Texas Instruments SN74AUC1G125DBVR, as these low-voltage variants have a typical propagation time as low as 1.5 ns. Figure 5 depicts my test board’s circuitry. I added plenty of series and parallel 49.9-Ω resistors, switchable thanks to jumpers, as well as several SMA connectors to easily measure the waveforms at different points of the circuit. A note on these test connectors: measuring a high-frequency signal without modifying the signal itself is not straightforward, even with a good oscilloscope. In fact, you have only two solutions. The first is to use a very low-capacitance active probe connected to the scope. Why a low-input capacitance? Assume that the line is 50 Ω and that you don’t want to modify its characteristics by more than 10%. That means that the impedance of the probe must be no lower than 500 Ω. You may think that this is easy as a standard oscilloscope input is 1 MΩ. But at high frequencies the parasitic capacitance of the probe is what matters. Even at 500 MHz a capacitor of 1 pF will have an impedance as low as 318 Ω!
Assuming that you don’t have expensive high-end active probes, the second solution, as shown in Figure 5, is to simply use a 453-Ω resistor. Connect it between the measurement point and a 50-Ω cable going to the input of the oscilloscope (configured as a 50-Ω input). This setup builds a well-matched 1:10 attenuation probe (as 453 + 50 is roughly 500, 10 × 50). The parasitic capacitance will stay very low as long as the 453-Ω resistor is surface mounted and very close to the point to be measured.
As a transmission line between the two gates, I drew a 20-cm track on a PCB. I used the great and free AppCad software to calculate the required track geometry for a 50-Ω characteristic impedance using the so-called coplanar waveguide structure (see Figure 6). Then I spent an hour or so to design the double-sided test PCB illustrated in Figure 7. If you aren’t familiar with RF PCB techniques, refer to my 2011 article, “RF and High-Speed PCBs: How to Avoid Basic Mistakes” (Circuit Cellar 253, 2011).
A week later I received the PCBs, it was time to check if the theory was right. Fortunately, my company received at the same time its impressive new oscilloscope so I couldn’t resist using it. It might make you jealous to know that it’s a Wavepro 813Zi-B from Teledyne Lecroy. This monster has four input channels, each with a real-time sampling rate of 40 Gsps and a bandwidth up to 13 GHz! It has also a built-in Intel core i7 quad-core 3.1-GHz processor and eats up to 1 kW of power, but that’s another story. OK, you may not need something as expensive to play with signal reflections, but it was too cool to switch it on. Photo 1 shows you the test board connected to the scope, with an old Hewlett-Packard pulse generator as a data source and a TTi power supply set to 2.5 V to power the logic gates.
As a first step, I removed all series and parallel resistors, simulating a direct interconnection of two logic gates through a 50-Ω transmission line. The measured waveforms are shown on Figure 8a. As expected, I got staircases. If you look closely, you will see that the voltage on the source end (blue) rises first, but to 1.5 V only. Some 1.5 divisions later (3 ns, one propagation time), the signal on the load side (green) climbs as expected to 2.5 V. And 1.5 divisions later the source signal jumps as expected to 2.5 V. There is another reflection as the load signal shows a small dip in the center of the screen, 1.5 divisions later. Very close to the predictions, assuming that the source impedance is a little lower than 50 Ω, isn’t it?
What happens if I add a small series resistor on the source side, here 22 Ω? Look at Figure 8b. It is very close to the former, but now the dips on the load side are significantly reduced, thanks to the added series resistor. The waveform on the source side stays a staircase as expected.
Lastly, adding a 50-Ω parallel resistor between the input of the load gate and the ground gives a very clean signal both on the load and source sides (figure 8c), at the expense of slightly reduced voltage levels.
Here we are. I hope that this short journey into the world of digital line terminations was enjoyable. If you want to learn more, I strongly recommend the excellent book, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (Wiley-IEEE Press, 2000). The authors—Stephen Hall, Garrett Hall, and James McCall—work for Intel and know what they are talking about. I highly recommend it!
Once again, don’t hesitate to experiment by yourself. The spreadsheet is a starting point, but you can perform some interesting experiments even with a lower-range oscilloscope. For example, if you have a 50-MHz oscilloscope, just replace the 20-cm transmission line by a 20-m roll of 50-Ω cable for an easy way to measure propagation delay of about 100 ns. With experimentation, reflections will no longer be on your darker side!
S. Hall, G. Hall, and J. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Wiley-IEEE Press, 2000.
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • APRIL 2016 #309 – Get a PDF of the issue