Planning for a Successful Analog ASIC Experience
Thus far, Bob has introduced analog ASIC technology and described three competing design methodologies (see Part 2) that offer unique sets of advantages and disadvantages. In this article, he covers the five key elements you need to explore before engaging an analog ASIC semiconductor company to design a custom chip.
Proper planning in anticipation of having an analog ASIC developed and produced for your company is not to be taken lightly. There are five key elements you need to explore internally before engaging an analog ASIC semiconductor company to design and produce a custom chip for you. Once you are comfortable with your internal analysis, you can then explore possible suppliers. If you’ve done the internal analysis correctly, you will have realized that there is much more to nonrecurring engineering (NRE) than the upfront costs your supplier will charge you for designing and tooling a custom chip. That’s the easy part, because it’s spelled out clearly in black and white in the contract you’ll be signing at the beginning of the project. There is a hidden part of NRE that few companies successfully quantify. And for good reason; it’s not easy. Let’s look at the five elements.
First, you need to accurately identify your existing bill of materials (BOM) costs. When asked, most customers simply get a list of components from their purchasing department along with the price they currently pay for them. But the real cost of your existing solution is higher than this. Less obvious are the “other” costs associated with these components. For example: purchasing costs, inventory costs, manufacturing costs (including labor costs, whether human or machine), cost per square inch of the PCB, or cost of lost production when there is an availability or quality problem from a supplier. This last one is really difficult to put a financial metric on.
Furthermore, and this is particularly true for analog, many discrete components such as resistors, transistors, diodes, and even capacitors can be eliminated by an analog ASIC. Consider as well the other side of the coin. There are new BOM costs associated with an ASIC. A new PCB layout is required. Perhaps additional qualification and reliability testing will be involved. All of these costs need to be scrutinized closely when considering a move to an ASIC solution. Be sure to quantify all the costs you will incur as well as all the costs you will save before committing. Ask your analog ASIC partner to assist you in understanding these costs.
Next, identify the availability of your resources to manage the transition from using many standard chips to a single ASIC. Someone needs to be the focal point when dealing with the ASIC company to field technical questions, define the electrical specification for the ASIC, conduct progress reviews and design reviews, manage the production change over, and much more. Program management does not necessarily require an additional headcount, but it will become a significant responsibility assigned to someone on the team. Be sure you have someone capable to assume this role and have a backup plan in case this person leaves your company in the middle of the project.
Understand the longevity and cumulative volume expectations of your product. There’s not much point incurring the effort to develop an ASIC if its lifespan will be short. There are, of course, obvious exceptions, such as applications in which the volumes are vast, as in mobile phones and computers. There, even if the lifetime of a chip is only a couple of years, the savings clearly justify the transition. I suspect most readers of this article can only dream of such volumes. The good news is that most analog applications typically have long lifespans and can easily support and justify the transition to an analog ASIC chip. Many industrial and medical applications can last 10 years or longer.
Don’t overestimate your volume expectations to try to lure an ASIC supplier into engaging with you. It is always better to underestimate; err on the conservative side. Analog ASICs do not require high volume. While everyone’s definition of “high volume” varies, to quantify it, many projects are successful at 25,000–50,000 units per year, even less when a tile array solution can be used. The days of 1 million, 500,000, or even 100,000 per year unit minimums are long gone. Analog ASICs have always been affordable to the masses. The problem has been that the masses never realized it. This is perhaps one of the single biggest misconceptions about analog ASICs.
As the customer, your responsibility is to manage as best you can the above four elements. The fifth element, risk, is shared. Both the customer and supplier must do all that is within their power to mitigate risk. Analyze the risks associated with ASIC development on both sides. What if your volume expectations aren’t realized? What if your analog ASIC supplier is unable to meet their completion date? Or worse yet (as is all too often the case), what if your supplier doesn’t really have the resident analog skill sets to meet all your technical requirements? Last-minute requests for waivers can kill your entire project. You can avoid this by getting to know the leader of the ASIC design team that will be assigned to your project. Assess for yourself their skills and understanding of analog chip design. Avoid language barriers. Make sure they fully understand your application. Encourage frequent meetings, phone calls, and Skype sessions.
Sometimes you need to make a change to the design midway through the ASIC development process. As unpleasant as it is, it happens all too frequently. Things go wrong. Requirements or markets can change unexpectedly. Make sure both you and your analog ASIC supplier understand this and have a corrective action plan. There may be additional charges, depending on the changes you are requesting and how far along your supplier is in the design process. Don’t throw your hands in the air and give up. Your supplier is as vested in the success of your analog ASIC as much as you are. Communicate quickly and efficiently to minimize any delays to the schedule.
NRE & TOOLING
Let’s now focus on NRE and tooling costs for the analog ASIC. This is where analog differs greatly from digital in the ASIC world. When specifying and designing analog ASICs, there is significantly more custom engineering involved. It also means that much more care and consideration must be put into the budgetary proposal being prepared for the customer. The ASIC supplier needs to know everything there is to know about the design: its application, its environment, its system architecture, and more. Back and forth technical Q&A takes place between the lead analog ASIC designer assigned to the project and the customer’s point person. This process of thoroughly understanding the customer’s needs can take weeks (sometimes months if the requirements of the analog ASIC are very complex) before a legitimate proposal can be offered. When quoting a moderate to complex analog ASIC, the ASIC supplier may invest $10,000 to $20,000 of their own resources just to provide a proposal. They should not be charging you for this effort. It’s part of the cost of doing business. However, sometimes it is necessary to actually do some circuit design of the ASIC to confirm that what the customer is requesting can actually be achieved. This should be discussed in advance before any “for money” effort is approved.
Moreover, while the ASIC design manager is evaluating the basic ASIC itself, another design team at the analog ASIC semiconductor company is looking into how this chip is going to be tested. What levels of precision are needed? Are there any special needs such as data acquisition functions? What power management blocks are involved? Are there any special noise requirements? Are there any special power-up sequences? Are there any high-voltage requirements that need to be addressed? At the end, does a special analog tester need to be designed and built specifically for this chip?
The costs of the NRE and tooling can vary greatly from design to design. Variables include the design complexity (man hours required to design and layout the chip), mask costs (determined primarily by the lithography of the wafer process: 0.18, 0.35, 0.5 µm, etc.), wafer costs—determined in part by the wafer size (150 mm, 200 mm, etc.)—and by special needs (number of layers, SOI, cavity etch for sensors, etc.). Your analog ASIC supplier will review with you any options and trade-offs you may wish to consider that might help minimize any of these costs.
Another thing to consider is whether or not your analog ASIC supplier offers any NRE and Tooling Rebates. Ask your analog ASIC supplier if they have a rebate program for the up-front costs associated with developing the chip. Although less frequent with a first time customer, rebates are an enticement to keep good customers returning with additional analog ASIC opportunities. When calculating your internal rate of return (IRR) for the ASIC investment, an NRE/Tooling rebate can dramatically alter the outcome in favor of the development. Rebates essentially have the effect of making the front end costs disappear over time as production is consumed. Rather than treating the upfront fees as a sunk cost, rebates allow your finance department to recover these costs over time.
A quick-and-easy approach to determining the financial viability of engaging in an analog ASIC project is to analyze the possible return on investment the project will bring. In the example below, I use IRR. It’s a simple and easy way to approximate the return your project will yield. It is simple because there is a built-in macro in Excel to calculate it. It works well for comparing potential yield from competing alternative uses of capital. Your finance department will undoubtedly use more sophisticated tools like modified internal rate of return (MIRR) for final decision making, but this simple IRR approach at least gives you a sense of whether or not you should even approach presenting an investment in an analog ASIC to corporate management.
Using the industrial power supply example discussed in Part 1 of this series, we can compare the simple IRR with and without a rebate. Recall that the BOM was reduced from $5.90 to $2.60, a savings of $3.30 per supply and forecasted volumes were 100,000 per year. The analog ASIC NRE and tooling costs were $327,000. To calculate a more realistic IRR, we must include those forecasted ancillary costs associated with the redesign of the PCB, complete quality and reliability testing, and other miscellaneous costs. In this example, we assumed it would be $200,000. In keeping with the customer’s estimate that production of this model would last another five years, the return is assumed to occur only during the four years (two through five).
Simple IRR calculations can be created using an Excel worksheet. Create a column of expenses and savings then enter the formula =IRR(D2:D7). Refer to Table 1. However, this customer did qualify for a partial rebate and the value of the rebate has been factored in (see Table 2). Accounting for possible NRE and tooling rebates increases the IRR by five points in this example. If the expected lifetime of the power supply were longer, the cost savings would be extended over more than just four years. For example, if the analog ASIC remained in production for five years, IRR would be 45%. At six years, it would be 48%. And at seven years, it would be 50%.
Supporting all of this is production capability. During this proposal development phase, the ASIC design manager also investigates the realm of possible wafer fabrication processes that are suitable to produce your design, selecting the one she/he feels is a best fit solution. The IC will be designed to meet your specific requirements as well as those of this silicon fabrication process. With rare exceptions, silicon fabrication processes cannot be changed or modified. The burden is 100% on the ASIC design team to get it right.
If you remember only one thing from this paper, it is this: never separate design from production. Do not use one company to design your analog ASIC and another company to manage your production. This is a recipe for failure unless you have an in-house team of “gray-haired” analog IC designers; otherwise, you are setting the stage for conflict when something goes wrong. Is it a design problem or a manufacturing problem? Unless your analog ASIC supplier is developing or modifying a process, if a performance issue arises in the initial silicon samples, 99 times out of 100 it will be a design problem. Yet independent analog design houses, those that do not offer production capability, will argue the contrary, saying the silicon was misprocessed and you, the customer, are stuck in the middle. This is not where you want to be. Even if you have lots of experience managing the backend for digital ASICs, you should always use a full service or turn-key supplier for analog ASICs.
Another reason for keeping the analog ASIC design and manufacturing under one set of hands is to ensure that your design is produced on an analog silicon process and not a digital process. Unlike digital ASICs, analog designs are extremely difficult (dare I say impossible?) to retool to a fabrication process other than the one they were originally designed for without doing a major redesign or re-layout of the chip. For this reason, selection of a reputable foundry, one with a solid track record of analog IC production, is paramount. During the chip’s design phase, the ASIC design team also considers the longevity of the process being selected. Is it well established—meaning, has it been in production for a long time and has it been proven to be reliable? Does the silicon foundry have considerable volume running on this process such that its likelihood of being discontinued is zero? All of the above helps you to mitigate the risks.
Once you have accepted the analog ASIC development and production proposal, a detailed specification of the IC is generated. This specification is similar to a typical semiconductor datasheet in terms of its contents. There may be a brief description of the IC, and a definition of the maximum operating limits (temperature, voltage, etc.) followed by a detailed electrical specification. The accuracy and completeness of the electrical specification is critical because this is what is used to define accept/reject criteria for the ASIC. The electrical specification becomes a part of the development contract, usually as one of several “exhibits” attached at the end of the contract. It is not unusual for minor changes to be made to the electrical specification (but only by mutual agreement) during the development of the chip as one side or the other notices things that may be mutually exclusive, or as one side discovers a means by which the chip can be further improved or reduced in size.
When the electrical specification is finalized and the contract is signed, development begins. Weekly, sometimes daily, discussions between the ASIC supplier and customer keep both sides in synchronicity throughout the development period. Periodic milestone reviews are held as well as a final signoff review, at which point the design is declared finished and the hard tooling/wafer fabrication phase begins.
Once the silicon foundry has produced the photolithography masks, they will begin wafer production. Throughput can vary from eight to 12 weeks before a finished wafer is delivered back to the ASIC supplier for testing. If all goes according to plan, the ASIC supplier will have the test system finished and awaiting wafers to test. Thanks to the skills of experienced analog design engineers, 99% of analog ASIC designs are fully functional in this first look. However, with analog, almost all designs will require minor tweaks to achieve complete parametric compliance with the specification. This is true for all standard product analog ICs as well. Although analog design and verification tools from companies like Cadence, Synopsys, Mentor Graphics, and others continue to improve, none are perfect. Still, a lot can be learned from a functional part. Samples are prepared and sent to the customer for evaluation. Any nonconformities or performance nuances are noted and normally corrected with a minor tweak to the metal interconnect layers of the chip. Upon verification by the customer, the revised chip is released to production.
Advanced planning, thoughtful and proper resource allocation, intimate understanding of your supplier’s analog design and production skills, a well-defined objective specification, and more will ensure the success for your project.
When it comes to analog, there are no shortcuts. If you insist on beating up your chosen supplier to quote shorter and shorter development times, it may backfire on you. Although delivery of first samples sometimes occurs in as little six to eight months, realistically you should expect it to be closer to 10 to 12 months and even longer for very complicated designs. Individual quotes will vary.
Think about your IP. If your design is simply an amalgamation of off-the-shelf standard products with no inherent invention in the design, you might not care. But if the chip will be containing your own proprietary IP, check very carefully as to where your chip will be designed. Yes, engineers in the United States and European Union might be costlier, but what are the costs to you and your business if your design is stolen? Reference my earlier comment about the Apple watch.
The same holds true for wafer fabrication. If you are at all concerned, insist that the product be fabricated where the rules of international law apply. Don’t be pennywise and pound foolish. When having an analog ASIC made for you, be very thorough about whom you select to design and build it as well as whom they select to do the wafer fabrication. The cheapest solution may not be the best solution. Analog is best left to the experts.
PUBLISHED IN CIRCUIT CELLAR MAGAZINE • NOVEMBER 2016 – Get a PDF of the issueSponsor this Article
Bob Frostholm (email@example.com) is Vice President of Marketing and Sales at JVD Analog ASIC Semiconductors in San Jose, CA. He has held sales, marketing, and CEO roles at established and startup analog semiconductor companies for over 40 years. Bob was one of the original marketers behind the ubiquitous 555 timer chip in the early 1970s. He is the author of several technical articles and white papers.