Basics of Design Research & Design Hub

All About Analog ASICs (Part 2)

Written by Bob Frostholm

Shrinking Size, Protecting IP, and Lowering Costs

Bob started this series by introducing analog ASICs and describing many of their advantages. This month he covers some of their additional benefits, including space savings, IP protection, and performance improvements. He also introduces three competing design methodologies.

  • How analog ASICs help with saving space, IP protection and lowering costs

  • What are the trade-offs between different analog ASIC creation methods?

  • How the cell approach works

  • How hand-crafted analog ASIC design works

  • How the tiled array method works

  • Analog ASICs

In the first part of this series, I offered some insight into the world of analog ASICs and cited some specific examples of cost savings that are realizable through integration. While probably the single largest motive for developing an analog ASIC, cost is not the only driving factor behind this rapidly growing segment of the IC market. Protecting intellectual property (IP) and reducing the size of your product are critical attributes that analog ASICs offer as well.


You’ve invested a lot of time and money creating your product, especially that part of your design where “Black Magic” prevails—the analog sections. You know this is where the rubber meets the road; where you can definitely show meaningful product differentiation. There is nothing more frustrating than spending months, perhaps years, and bucket loads of money developing a product only to discover that after it’s been in the marketplace for six months or so, some bandit has stolen your design, copied your product, and is selling it to your customers. To make matters worse, because he has little or no development costs to recover, he’s selling it at a substantial discount to your price.

Protecting intellectual property is one of those intangible reasons for considering an analog ASIC. It’s like buying the insurance package at the Big Box store when you purchase that new 75″ 3-D flat panel SMART TV. Is it really going to fail? Is it worth the cost of the insurance just in case, even though it will increase the cost of the TV? There are no easy answers to these questions. The law of averages says you’re wasting your time/money in doing so, unless you’re that one in 5,000 who has a problem and your TV dies.

The same argument can be applied to using an analog ASIC to protect IP. What are the odds that your product will fall victim to a product pirate? Only you can answer that question, and only you can determine the financial damage a pirate can do to your business. Remember the long-awaited Apple watch? Prior to its introduction, copies were already being offered for sale in China. Companies like Apple are prime targets for product pirates because their volumes are huge, product value is high and demand remains very strong over a long period.

In highly competitive markets, players slug it out on one of two fronts: technical differentiation or price. If you have no technical differentiation, your product is doomed to a lifetime of low profit margins as you desperately try to lure customers into your camp with discounts. If you do have technical differentiation, you need to do everything possible to protect it from falling into the hands of the pirates. Patents may offer some benefit, but in many countries where the rule of law carries less weight than in the US, you might be in for a big surprise.

A product embodying standard off-the-shelf analog ICs offers no protection from being copied. Distribution systems are global and any standard part can now be sourced in any country. Compounding the situation is the sad fact that most standard product semiconductor manufacturers offer their chips for sale in Asian countries at prices lower than right here in the US, putting you at a further disadvantage. This has long been called the China price, and buyers there are not shy about reminding suppliers of their expectations of receiving the absolute lowest pricing.

Moreover, if your volumes are only small to moderate, you won’t gain the attention of the larger, more reputable offshore subcontract assemblers who have purchasing power in Asia to get you similar pricing. This further endangers your product’s potential for copying. By using an analog ASIC chip in your design, you can prevent the product pirates from copying your design. The ASIC will be produced and sold exclusively to you. Some US OEMs will source all their components and assembly off shore with the exception of the analog ASIC which they control carefully by sourcing domestically and then ship controlled quantities to the subcontract assembler. Think of it as “trust, but verify.” Since the analog ASIC has no published datasheet, pirates will have no means of ascertaining what functions are included in the chip or what specifications are being met. If they can’t figure out how your product works, they can’t copy it. Protect it with an affordable analog ASIC.


In a world of wearable sensors and the Internet of Things (IoT), size does matter. Nowhere in your product is there a greater opportunity to conserve space than in your analog circuitry. Bulky, single function, off-the-shelf standard product analog ICs consume more than their fair share of board space. Frequently, systems require simple gain stages that amount to a handful of transistors, yet in the actual end product a designer has incorporated an op-amp in an eight-pin package. An implementation with discrete transistors may be about the same size footprint. But when added to a chip that already includes several other analog functions, the gain stages are so small, they are basically free.

If size is an issue, a well thought out analog ASIC might just be the answer you’re looking for. Plus, analog ASICs can absorb more functionality than you might think. Combining multiple standard analog ICs into an analog ASIC often reduces the need for peripheral passives like resistors and capacitors. Let’s look at Example 2 from Part 1 of this article series. Photo 1 shows the original analog PCB implementation of a wireless automotive diagnostics system before and after analog integration. By integrating the components discussed in Example 2 earlier in Part 1 of this series, the size of the PCB was reduced to allow a form factor suitable for installation into the OBD-II connector (located under the dash near the steering column in most cars) without physically interfering with the safe operation of the vehicle. Without analog integration, it would not have been possible to produce this product.

There are two basic ways to create an analog ASIC and a third less popular and costlier (unit ASP) approach. Advantages and disadvantages to each approach are summarized in the table in Table 1. In the following sections, I’ll present each approach.

Photo 1 The analog card (left) contains transceivers, multiplexers, and power management chips that were integrated into a small analog ASIC (right) allowing the wireless diagnostic tool to achieve an acceptable form factor.
Photo 1
The analog card (left) contains transceivers, multiplexers, and power management chips that were integrated into a small analog ASIC (right) allowing the wireless diagnostic tool to achieve an acceptable form factor.
Table 1 Comparative analysis: cells versus hand-crafted analog design
Table 1
Comparative analysis: cells versus hand-crafted analog design

The most common approach to designing an ASIC is by using a cell library. Initially created for digital ASICs, most digital dell libraries today also contain rudimentary analog functions as well as all the basic Boolean algebra digital functions. Think of a cell library as a data book or product catalog. A large semiconductor company may have an online catalog containing thousands of different ICs for you to choose from when designing your product. Silicon foundries, sometimes called wafer fabs, are used by fabless semiconductor companies to produce their designs. To encourage fabless semiconductor companies and companies who just do chip design without production to bring business to them, these foundries offer their own product catalogs called cell libraries.

A cell in a library is a collection of pre-designed functional blocks, groups of transistors and sometimes resistors that are interconnected to provide basic Boolean logic functions (e.g., AND, OR, XOR, XNOR, inverters, etc.) or a storage function (flip-flop or latch). Some libraries also include basic analog cells such as simple amplifiers, comparators, voltage references, etc. These predesigned pieces of commonly used circuitry are available to chip designers to copy and insert into their designs to expedite the development process and lower development costs. The concept is flawless, but execution can be a different situation.

Many ASIC companies rely almost exclusively on this copy and paste method of designing an IC. Here’s the rub. The choices for analog functions in any given library are very limited. Cell libraries primarily serve the digital IC market, not the analog IC market. Companies that offer mixed-signal ASIC designs are more focused on the digital aspect of the design process and rarely have a staff of experienced analog IC designers available to intervene when problems occur in the analog signal chain.

To compound the problem, analog libraries are designed by a different team of engineers than those who use them to create an ASIC. The mixed-signal ASIC chip designer that you may have contracted with to design your chip often has no first-hand knowledge of what’s going on inside the analog cell. It’s no different that you are picking a part out of a data book. Except if you choose the wrong part, changing a PCB to accommodate a different analog IC is far less costly (in terms of time and money) than having to redesign an ASIC.

An even greater disadvantage comes from the lack of choices when using a library. Your choices are severely limited, and for each function, you must select not the perfect fit (because it isn’t always available), but the closest fit. Maybe your design needs a reference with 25-ppm stability but the closest available reference cell in the library is 35 ppm. You’ve just introduced error into your design.

ASIC designers using analog cell libraries face this problem continually and must weigh the risks of compromise. Compromise results in errors and errors accumulate to the point where the end chip often fails to meet its full product specification (see Figure 1). The ASIC designer selects a cell from the library based on the specs that she/he feels will be a best fit for the requirements and inserts it as a predesigned entity in their circuit. As the design progresses, errors accumulate and frequently the first pass silicon chip must be redesigned in part to correct for these errors. Re-spins are costly in terms of both money and time to market of the end product.

Figure 1 Continuous use of best-fit cells can lead to a product that fails compliance to the desired specification
Figure 1
Continuous use of best-fit cells can lead to a product that fails compliance to the desired specification

The cell approach can save considerable development time because the performance of that cell has already been proven. By combining a number of such cells, an analog subsystem can be quickly created in the ASIC using these basic building blocks. Another serious drawback when using analog cells is that, unlike digital cells that stack tightly together, analog cells often don’t and a chip layout can result in lots of wasted space, as shown in the exaggerated representation in Figure 2.

The cell library approach is suitable for creating an analog ASIC where precision and accuracy are less important. All that is needed are basic gain functions, voltage converters, simple references, etc.


The second approach is to individually design each function that will be a part of the analog ASIC: op-amp, A/D converter, voltage regulator, etc. This technique is referred to as “hand-crafted.” It relies on the ASIC design engineer being a true analog IC design expert. The problem is that our colleges and universities are not producing analog designers. Just look at the curriculums offered. Their focus is mainly on computer science and digital design classes. Every major standard product analog IC company complains about this. Analog Devices, Texas Instruments, Linear Technology, and Maxim (to name a few) hire the best and brightest engineering graduates and then invest decades to develop their levels of expertise to make them great at hand-crafted analog IC design.

To ensure you’re accessing the best possible analog design skills when considering a hand-crafted approach, seek out analog ASIC companies collocated in these centers of analog excellence (locations known for hosting well-established standard product analog IC companies like Austin, Boston, Dallas, Phoenix, and, most notably, Silicon Valley). Expert analog IC designers are “created” within the confines of companies like these. But entrepreneurial spirit springs eternal and dozens of analog ASIC companies have started up within arm’s reach of these magnificent firms. Apples don’t fall very far from the tree. These communities offer the best prospects for success with analog design because within these analog design communities is a very tightknit network—one in which every guru knows all the other gurus and references and referrals abound. Experts in particular analog fields can be contacted and consulted easily.

A hand-crafted analog IC design from these luminaries and their disciples far exceeds the performance from cell-based solutions. Remember, analog is described by a set of mathematical equations—digital by Boolean relations. Analog IC designers must be expert in maintaining and perfecting signal integrity by crafting how it’s done rather than being content with knowing what is being done.

An advantage of hand-crafted analog ASIC designs is the intimacy between the chip designer and the application. Unlike cell-based design approaches which inhibit creativity, hand-craft analog designers are able to add tremendous value to the development process by offering insights into ways in which the system performance can be improved. They are also constantly on the lookout for subtleties that can introduce errors, even if only under the most remote circumstances (see Figure 3).

Figure 2  Visual comparative analysis: analog cells versus hand-crafted
Figure 2
Visual comparative analysis: analog cells versus hand-crafted
Figure 3  Hand-crafted analog ASIC design is an iterative process in which cause and effect are constantly being juxtaposed, allowing the IC designer to "tune" the circuit for 100% specification compliance during the design.
Figure 3
Hand-crafted analog ASIC design is an iterative process in which cause and effect are constantly being juxtaposed, allowing the IC designer to “tune” the circuit for 100% specification compliance during the design.

A third ASIC design approach uses a tile array of analog functional blocks. The first company to offer this semi-custom approach was InterDesign, back in the early 1970s. Founded by Hans Camenzind, the noted inventor of the ubiquitous NE555 timer chip, InterDesign was perhaps the first semiconductor company to focus exclusively on the design and manufacture of semi-custom integrated circuits. InterDesign offered a variety of prefabricated ICs containing basic analog blocks like op amps, comparators and arrays of resistors. Customers were given tools with which to show how they would like to configure these blocks to form a small analog system on a chip. InterDesign would then fabricate the final wafer metal mask, unique to that customer, which would connect the blocks according to the customer’s request. The methodology is still available today with far more sophistication in terms of the available blocks on the silicon chip and the means of making the final interconnections. It’s a great solution for applications that are very low volume and insensitive to unit cost.


Analog ASIC designs using cells and tiles provide basic functionality and can be adequate for many applications. Custom or hand-crafted analog ASIC design can be more cost effective over the long term, and it delivers better performance and higher rates of specification compliance than any cell library. Designing critical analog requirements with cell libraries is like designing a race car with Legos.

Several competing design methodologies are available with which to create an analog ASIC semiconductor. Before embracing any one approach, take the time to evaluate your needs and how best they will be fulfilled. In the third and final part of this article series, we will discuss what you, the OEM, need to do internally to prepare for an integration project to ensure success. 

Read Part 3 Here


Keep up-to-date with our FREE Weekly Newsletter!

Don't miss out on upcoming issues of Circuit Cellar.

Note: We’ve made the Dec 2022 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

Would you like to write for Circuit Cellar? We are always accepting articles/posts from the technical community. Get in touch with us and let's discuss your ideas.

Sponsor this Article
Vice President of Marketing and Sales at JVD Analog ASIC Semiconductors in San Jose, CA | + posts

Bob Frostholm ( is Vice President of Marketing and Sales at JVD Analog ASIC Semiconductors in San Jose, CA. He has held sales, marketing, and CEO roles at established and startup analog semiconductor companies for over 40 years. Bob was one of the original marketers behind the ubiquitous 555 timer chip in the early 1970s. He is the author of several technical articles and white papers.

Supporting Companies

Upcoming Events

Copyright © KCK Media Corp.
All Rights Reserved

Copyright © 2024 KCK Media Corp.

All About Analog ASICs (Part 2)

by Bob Frostholm time to read: 11 min