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Xilinx has Three Automated Test Equipment Lines for Semiconductors

Written by Stephen Vicinanza

Xilinx has three automated test equipment lines for semiconductors. The three areas that Xilinx focuses on for next-gen SoC testing cover: SoC and storage testers, semi-ATE: image acquisition, and semi-ATE: PIN electronics.

SoC and Storage Testers

The Versal architecture gives system designers performance, power-optimized hard IP, and flexibility that are exclusive to Xilinx. DSP engines and AI engines, available in the Versal Premium ACAPs provide unmatched signal processing capacity. Featuring on/off-chip memory bandwidth at higher speeds. There are 7.5M system logic cells in the Adaptable Engines, that play a critical role in developing ATE the flexibility necessary for custom IP, monitoring functionality, and traffic generation.

Additionally, the scalable 112G PAM4 transceivers and power-optimized Hard IP are pre-engineered to enable the most popular interface standards, including a variety of performance options and features. Some of the likely candidates for such systems measurements are the 400G High-Speed Crypto Engines, 600G Ethernet MAC, Integrated PCIe Gen5 Blocks, DDR Memory controller, and more.

Semi-ATE: Image Acquisition

Xilinx offers the Kintex UltraScale+ to cover the need for high-performance transceivers and DSP capability for Image Acquisition. The system also keeps power consumption and device cost low. The cost-sensitive nature of this application requires special attention to power consumption.

The Kintex UltraScale has a solid price/performance/watt balance delivering a cost-effective solution for high-end capabilities that include support for such systems as 6.3 TeraMACs of DSP compute performance, PCIe Gen 4×8, 2.6Gbs DDR4, and 32Gbps transceivers.

Semi-ATE: PIN Electronics

For vector generation and analysis, there is a need for cost-effective FPGAs to address PIN Electronics. This would also include a large number of high-performance I/Os to connect to a greater number of ASSPs with their parallel interfaces. There is a need for sophisticated I/O buffers and more capable clock generation and distribution given the 1Gb/s+ link speed, fewer reference clocks, and unfriendly channel, to manage skew across multiple lanes and over PVT.

The Kintex UltraScale+ FPGAs have feature-rich SelectIO transceivers and are high-performance. The SlectIO transceivers have signal conditioning capabilities, PLL and DLL-based clock generation as well as distribution resources. These are enhanced with skew management capabilities.

To find out more about the Xilinx line of semiconductor automated testing equipment see the products page here.

Xilinx |

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For the past 8 years, I have been writing about embedded technologies, added to my technical, academic, and medical editorial experience, with companies like Elsevier and Cambridge University Press. I tell people to read what I write, not try to pronounce my last name. I am always available for comments and suggestions you can reach me at and I promise I will take the time to reach back out to you. I live in the North East with my wonderful family.

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Xilinx has Three Automated Test Equipment Lines for Semiconductor…

by Stephen Vicinanza time to read: 2 min