Just announced several days ago, Telechip to license Arteris FlexNoC for use in advanced automotive applications.
Arteris In. announced that FlexNoC (Network on Chip) Interconnect IP would be used in collaboration with Telechip to help speed the creation of System on Chip (SoC) products Telechip is producing. These products are based on the latest automotive safety standards, including ISO 26262, ASIL B, and D.
The products are likely to find their way into applications where security is a concern, such as advanced driver-assistance systems (ADAS) and Microcontroller Units (MCUs).
“Advanced SoCs require best-in-class network-on-chip technology for low power and safe connectivity,” said K. Charles Janac, president and CEO of Arteris. “We are delighted that, in the advanced SoC automotive market, Arteris products continue to be the leading choice for high-performance, innovative solutions.”
“Telechips excels at building SoCs that offer a solution for various automotive applications with superior performance, low power, and security, especially for functional safety,” said Moon Soo Kim, SoC group leader and VP of Telechips. “Arteris’ proven to interconnect IP technology ensures that we meet our design requirements to facilitate safety and scalable future products, helping us to drive global innovation trends. And, it will help our new business areas, especially ADAS and MCUs, meet the highest level of OEM and Tier 1 requirements.”
The FlexNoC reduces wiring by about 50%, in new builds. Whether that build is proprietary or AMBA, AXI3, AXI4, AHB, OCP or APB, the FlexNoC is working to reduce time-to-market on SoCs. There are intuitive GUI, and scripting interfaces. Support that is right out-of-the-box coverage, for all IP transaction protocols. This makes changing an IP or making changes to the IP to create SoC derivatives easy, even late in the development process.
With a fast performance validation process using the FlexExplorer simulation. The explorer generates OSCI SystemC TLM 2.0 interconnect models. This is handled at three levels of abstraction, speeding up turnaround times in the performance evaluation of the interconnect configuration.
For further information, there is a datasheet found here. And a peer-reviewed technical article previously published in Springer “Design Automation for Embedded Systems Journal” can be downloaded for free here.
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