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SEGGER Dev Tools Provide Codasip RISC-V IP Support

SEGGER and Codasip have announced that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box. SEGGER’s J-Link debug probe supports RISC-V debug on Codasip’s processor cores. Furthermore, J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries are perfect for minimizing code size.

Codasip’s family of 32-bit embedded processors (names beginning with “L”) and 64-bit embedded processors (names beginning with “H”) are based on the RISC-V Instruction Set Architecture (ISA) and can be customized to meet domain-specific requirements.

Codasip provides leading-edge RISC-V processor IP and high-level processor design tools, providing IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to customize the processor IP. As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip says it is committed to open standards for embedded and application processors.

Codasip | www.codasip.com

SEGGER Microcontroller | www.segger.com

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SEGGER Dev Tools Provide Codasip RISC-V IP Support

by Circuit Cellar Staff time to read: 1 min