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Reduced Code, IAR Embedded Workbench for RISC-V from Andes

Written by Stephen Vicinanza

IAR Embedded Systems has released the IAR Embedded Workbench for RISC-V for the CoDense extension of the Andes Technology AndeStar V5 RISC-V processor.

CoDense is an extension of the processor’s Instruction Set Architecture (ISA) which helps the IAR toolchain provide compact code. This saves flash memory on the target processor. While that is happening the previously supported AndeStar V5 DSP/SIMD and Performance extensions help to provide better overall performance in the application.

IAR had already been involved by supporting the AndesCore RISC-V CPU IP at an early stage offering users the complete development toolchain. This included the IAR C/C++ Compiler and a comprehensive debugger, which is also included in the ISO 26262 conforming functional safety certified edition.

Andes Technology is a founding Premier member of RISC-V International. They are a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. The team up of Andes and IAR has created a robust design methodology for safety applications. This is also helping developers accelerate time-to-market by shortening the certification process.

The CoDense extension is a feature in AndeStar V5 for code size compression on top of the extensible RISC-V standard ISA. This extension has been proven in more than 10 billion SoCs with the previous AndeStar V3 processors.

“We are glad that IAR Systems provides full support to AndeStar™ V5 RISC-V processors, especially
including the enhancement of the patented CoDense™ extension in this release,” said Dr. Charlie Su,
President and CTO of Andes Technology. “CoDense™ increases the code density by double digits and is very welcome in MCU or IoT applications. We look forward to the competitive combination of IAR Embedded Workbench with AndeStar™ V5 RISC-V extensions with up to 30 percent higher performance made available to the RISC-V community.”

“Thanks to our close cooperation with Andes, we provided early support for the AndeStar™ V5
DSP/SIMD and Performance extensions and now full support for Andes CoDense™, enabling code size compressions on top of RISC-V C-extension,” said Anders Holmberg, CTO at IAR Systems. “The
the balance between code size and performance can make a real difference in the total return on investment from a product or project. With CoDense™ support, we give our users the power to tip this balance in their favor.”

IAR Embedded Workbench for RISC-V can be found on their website here.

IAR Systems |

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For the past 8 years, I have been writing about embedded technologies, added to my technical, academic, and medical editorial experience, with companies like Elsevier and Cambridge University Press. I tell people to read what I write, not try to pronounce my last name. I am always available for comments and suggestions you can reach me at and I promise I will take the time to reach back out to you. I live in the North East with my wonderful family.

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Reduced Code, IAR Embedded Workbench for RISC-V from Andes

by Stephen Vicinanza time to read: 2 min