NXP Semiconductors has announced the expansion of its EdgeVerse portfolio with its crossover applications processors, including i.MX 8ULP (shown) and i.MX 8ULP-CS (cloud secured) Microsoft Azure Sphere-certified families, as well as next-generation i.MX 9 series of high performance intelligent applications processors. The expansion includes new innovations with EdgeLock secure enclave to enhance edge security and Energy Flex architecture to maximize energy efficiency.
NXP has also introduced the EdgeLock secure enclave, a pre-configured security subsystem that simplifies implementation of complex security technologies and helps designers avoid costly errors. It enhances protection to the edge device by autonomous management of critical security functions, such as root of trust, run-time attestation, trust provisioning, secure boot, key management, and cryptographic services, while also simplifying the path to industry-standard security certifications. The EdgeLock secure enclave intelligently tracks power transitions when end-user applications are running to help prevent new attack surfaces from emerging.
The secure enclave will be a standard integrated feature across the i.MX 8ULP, i.MX 8ULP-CS with Azure Sphere, and i.MX 9 applications processors, providing developers with a wide range of compute scalability options to easily deploy security on thousands of edge applications.
Keeping an edge device secure long after initial deployment is a challenge that requires nonstop trusted management services. NXP partnered with Microsoft to bring this capability to its customers with Azure Sphere chip-to-cloud security in the i.MX 8ULP-CS (cloud secured) applications processor family. The i.MX 8ULP-CS with Azure Sphere incorporates Microsoft Pluton enabled on EdgeLock secure enclave as the secured root of trust built into the silicon itself, and as a key step toward enabling highly secured devices for a vast range of IoT and industrial applications.
In addition to the secured hardware, Azure Sphere includes the secured Azure Sphere OS, the cloud-based Azure Sphere Security Service, and ongoing OS updates and security improvements for over ten years. Azure Sphere chip-to-cloud security will be enabled on specific products within the i.MX 9 series, giving developers an even broader set of processor options to implement managed device security across more of their products.
Optimizing energy use at the chip level is becoming an increasingly crucial part of designing energy-efficient edge systems. NXP’s implementation of innovative Energy Flex architecture is designed to extend battery life and reduce energy waste in portable or plugged-in devices.
— ADVERTISMENT—
—Advertise Here—
In the i.MX 8ULP and i.MX 8ULP-CS families, the Energy Flex architecture delivers as much as 75% improved energy efficiency than its predecessor by uniquely combining heterogeneous domain processing, design techniques and 28nm FD-SOI process technology. Embedded in these processors is a programmable power management subsystem that can govern more than 20 different power mode configurations to deliver exceptional energy efficiency – from full power to as low as 30 microwatts. Using this range of flexible configurations, OEMs and developers can customize application-specific power profiles to maximize energy efficiency.
Building on the i.MX 6 and i.MX 8 series of applications processors, NXP’s i.MX 9 series debuts a new generation of scalable, high-performance processors. Scalable i.MX 9 families bring together higher performance applications cores, an independent MCU-like real-time domain, Energy Flex architecture, state-of-the art security with EdgeLock secure enclave, and dedicated multi-sensory data processing engines (graphics, image, display, audio and voice). The i.MX 9 series integrates hardware neural processing units across the entire series for acceleration of machine learning applications. It also marks NXP’s first implementation of the Arm Ethos U-65 microNPU, which makes possible building low cost, energy-efficient edge machine learning (ML). The first families in this series will be built in 16/12nm FinFET class of process technology with specific low power optimization.
NXP Semiconductors | www.nxp.com
