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The Future of DRAM for the IoT

Written by Hsiu-Min Lin

Why HyperRAM Works Best for IoT Designs

According to the mobility report published by Ericsson in June 2020 [1], technology used in massive IoT implementations—including NB-IOT and Cat-M—continues to be deployed around the globe. Due to the decrease in transportation because of COVID-19, the penetration of new IoT technology is lower than we expected. Most of IoT applications are still connected through 2G or 3G technology. In 2019, the estimated number of massive IoT applications tripled, and is expected to have reached approximately 100 million units by the end of 2020 when that data is collected.

As Ericsson estimates in its report, by the end of 2025 NB-IOT and Cat-M will account for 52% of all cellular IoT devices. The Asia region will be fastest growth market and volumes of devices in this region will increase to 67% of all shipments before 2026.

Meanwhile, progress on 3GPP cellular standards moves forward. 3GPP-Release 15 has enhanced the stability and application field regardless of NB-IOT or Cat-M. Release 16, which was just frozen in July 3, 2020, will strengthen further on network efficiency and deploy current NB-IOT to be operated in 5G environment. In the future, Release 17 will extend specification of bandwidth aggregation and of lower latency, continuing to develop and exploring potential application in order to stimulate cellular IoT penetration based on 5G NR foundation.

Semi Vendors Target IoT
For IoT applications, various design considerations—such as low cost, low power consumption, and computing efficiency—must be met in order to gain widespread adoption in the market. Especially for battery-powered devices, such as smart speakers and smart meters, battery life has become the key to the success of the product—in addition to factors such rich IoT functionality and easy-to-use human interface. All that makes low power consumption increasingly important. To achieve long battery life, using lower microcontrollers (MCUs) is important, but other low-power peripheral components—like memory—should be considered also.

Many mobile devices have the similar architecture in Figure 1. Similar basic block diagrams as this span devices ranging from tablets to smart watches. Wi-Fi, Bluetooth and cellular modules handline the communication in such devices. And sensors (like touch panel sensors) are dedicated to collecting outside information and feeding information to an application processor. NOR/NAND flash memory is responsible for storing code/data, while DRAM is fused or processing temporarily.

Figure 1
Block diagram of mobile device using HyperRAM

With all that in mind, many MCU suppliers are developing new-generation MCUs with higher performance and lower power consumption to meet the market demand. In addition, from the overall system design perspective, the DRAM that works with the MCU also requires new options to provide better advantages than those of the existing SDRAM, Low Power (LP) SDRAM and CRAM/PSRAM. All those DRAM standards were defined a long time ago, and haven’t kept pace with the latest IC process technology as Table1. HyperRAM, which supports the HyperBus interface, is a latest technical solution to address this demand. HyperBus technology was first unveiled by Cypress Semiconductor in 2014, and the company launched its first HyperRAM product in 2015.

Year standard published 1994 2007 2005 2019 (2.0) 2014 (1.0)
Logic process node when standard published 800nm 65nm 90nm 7nm
Table 1
Existing DRAM standards were defined a long time ago and have not kept pace with the latest semiconductor process technologies.

Benefits of HyperRAM
HyperRAM has only 13 signal I/O pins, which can greatly simplify PCB layouts. It also means that, when designing end products, MCU have more pinouts for other purposes, or it allows you to use MCUs with fewer pins for better cost-effectiveness. As Figure 2 shows, HyperRAM has fewest pins to achieve approximately the same throughput (333MB/s), compared to similar DRAM—like LPDRAM, SDRAM and CRAM/PSRAM.

Figure 2
Comparison of I/O pins

A simplified control interface is another feature of HyperRAM. PSRAM only has 9 states compared to 18 states of LPSDRAM. The fewer the flow states, the less complex your DRAM controller needs to be. For instance, based on PSRAM architecture, HyperRAM is a self-refresh RAM. Moreover, it can automatically return to standby mode. Therefore, system memory is easier to use, and the development of firmware and drivers is also simplified. Because HyperRAM has been developed in recent years, it is well suited to the newest semiconductor process nodes and package technologies. That means its package size is smaller other DRAM technologies.

Power consumption is critical to IoT devices because they are usually powered by batteries. Reducing power consumption not only saves energy usage, but also reduces the costs of recharging and of replacement. Consider Winbond’s 64Mb HyperRAM as an example. Its Standby power consumption is 90µW at 1.8V, while at that same capacity SDRAM is about 2000µW at 3.3V. More importantly, power consumption of HyperRAM is only 45µW at 1.8V in Hybrid Sleep Mode, which is a significant difference from that of the Standby mode of SDRAM (Table 2). On the other hand, even when LPSDRAM is used, power consumption and form factor are both still bigger than that of HyperRAM.

(Hybrid Sleep Mode)
Voltage 3.3V 1.8V 1.8V 1.8V 1.8V
Standby power 2000µW 400 µW 160µW 90µW 40µW
Table 2
Power consumption comparison

The HyperRAM Ecosystem
From the perspective of overall system design and product life, HyperRAM has become an ideal choice for emerging IoT devices. In addition to Cypress Semiconductor, leading MCU companies such as NXP Semiconductor, Renesas Electronics, STMicroelectronics and Texas Instruments have already released MCUs that support the HyperBus interface, and their new products will continue to support it in the future.

Meanwhile, development support for HyperBus’ control interface is readily available. Cadence and Synopsys have begun to provide HyperRAM memory verification IP, which can accelerate IC vendors’ design cycles. As a result, compared to other Octal RAMs, HyperRAM has the most mature application environment. HyperRAM has been incorporated into JEDEC standard, becoming a JEDEC-xSPI compatible technology.



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Hsiu-Min Lin graduated from Graduate Institute of Electronics Engineering, National Taiwan University and currently works in DRAM Marketing Division, Winbond Electronics as a Technology Manager. He is responsible for advanced technology, and serves as Winbond's representative in JEDEC committee meetings. Lin is also responsible for surveying new opportunities such as automotive applications. He serves as the safety manager (ISO26262) of Winbond Electronics' DRAM group.

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The Future of DRAM for the IoT

by Hsiu-Min Lin time to read: 4 min