Virtual prototyping has been making its appearance in the embedded software arena since the late 1990s, steadily gaining acceptance as a valuable software development target. It initially rode the wave of rapid advances in chip process technology, which enabled multiple programmable cores on a single chip. This triggered a domino effect in product capabilities, with deep convergence of multiple functions in the same device becoming possible (smartphones being the most idiomatic example). In the semiconductor business landscape, ASIC companies needed to grow into system-on-chip (SoC) companies. The force of growing software content, complexity in general and the specialized nature of the low-level SoC software specifically was amplified by increased time-to-market pressure. Traditional development practices (mostly post-silicon) and targets (physical boards, FPGAs, etc.) couldn’t answer the call for true pre-silicon software development. In its first decade, virtual prototyping has established itself as the key “shift left” enabler in SoC development.
During the past five years, virtual prototyping has silently enabled embedded software to get past key inflection points and challenges. In the mid-2000s, the introduction of multi-core architectures was a key hurdle for embedded software, requiring considerable refactoring of existing single-threaded/-core software stacks. Virtual prototyping’s debug and visibility advantages facilitated the transition. Around the same time, security hardware was introduced in leading mobile SoCs to provide the basis for a secure computing platform, enabling user services like mobile commerce. The complexity of the new security software and hostility of a physical target for development—a device is supposed to be hacking resistant—made a good case for virtual prototyping, which provided ample visibility into the complex secure/non-secure domain interactions and a less hostile development target.
More recently, we observed adoption to address the SoC power consumption challenge. Power efficiency correlates directly with longer battery times, and dedicated chip hardware, both on- and off-chip, was introduced to manage power. The hardware flexibility offered is large, with final control left to the software. Complex power management software layers were introduced in high-level software stacks, and as virtual prototyping uniquely allows for an accurate representation of the complex hardware clocking and voltage schemes (other technologies like FPGAs can’t easily tackle this), it not only became an enabler for this new development, but also proved its value in software optimization for power and energy.
Today virtual prototyping is powering the architecture transition from 32- to 64-bit in the embedded space, through its use for early instruction-set market introduction, by enabling the porting of large existing stacks prior to the first 64-bit physical implementation and by helping the SoC companies transition their software.
The above inflection points appear in different markets earlier than others, with mobile being on the leading edge of embedded software advances, typically followed by networking and automotive. For instance, automotive is only now facing the multi-core challenge. As such, virtual prototyping repeatedly will play a key role in tackling a specific inflection point.
Looking towards the future, the technology will make further advances on two major fronts: contribution to software quality testing and deeper anchoring into other parts of the SoC design flow, through integration with technologies like hardware emulation and FPGA-based prototyping. With its value for the development phase of software accepted, tackling the next phase, software testing, is natural. The software nature of virtual prototypes allows for large parallel deployment, ideal for regression testing. Moreover, with continuous integration now accepted as a regular practice in desktop and web software development, we expect the embedded market to follow this trend. And with a virtual target making continuous integration straightforward, we expect virtual prototypes to play an important role in the trend’s adoption. Markets including automotive (and mil/aero) have stringent safety and reliability requirements, and virtual prototypes’ unique fault injection capability is starting to show its value. Security testing and analysis is still an unexplored area, which not only has potential for the Internet of Things market, but can have a broad impact as security is becoming commonplace for any connected system.
Having simulation performance track the increasing SoC design scale and keeping the modeling effort under tabs to deliver value sufficiently early are not small engineering challenges. Just-In-Time compilation gave a major boost in the 2003–2004 timeframe, but the number of SoC subsystems requires another turbocharge right now. Exploiting the subsystem-level parallelism through new technologies that map subsystem simulations to different cores in the host machine, and deep-insight performance profiling tools that allow performance tuning, will carry the technology forward for another 5-10 years. Raising the modeling abstraction level, increasing automation and promotion of subsystem-based re-use and assembly methodology are effective arms to tackle the modeling effort challenge.
With its challenges being dealt with, virtual prototypes will continue to drive a further shift left and to converge with the numerous inflection point challenges of embedded software ahead. In 5-10 years, this embedded virtualization technology will likely be as accepted as virtualization technology is in the IT space today. A bright future indeed!
This essay appears in Circuit Cellar 299 (June 2015).