People want transistors—lots of them. It pretty much doesn’t matter what shape they’re in, how small they are, or how fast they operate. Simply said, the more the merrier. Diversity is also good. The more different the transistors, the more useful and interesting the product. And without any question, the cheaper the transistors, the better. So the issue is, how best to achieve as many diverse transistors at the lowest cost possible.
One approach is more chips. Placing a lot of chips close together on a small board will produce a system with many transistors. Another way is more transistors per chip. Keep on scaling the technology to provide more transistors in one or a few chips.
The third option combines these two approaches. Let’s have many chips with many transistors and end up with a huge number of transistors. However, there is a limit to this approach. It’s well understood that scaling is coming to an end. And placing multiple chips on a board can have a terrible effect on a system’s overall speed and power dissipation.
But there is an elegant and intellectually simple solution. Rather than connecting these chips horizontally across a board, connect them vertically, providing N times more transistors, where N is the number of chips stacked one above another. Such vertical, 3-D integration was first broached by William Shockley, co-inventor of the transistor at Bell Labs in 1947. Shockley described the 3-D integration concept in a 1958 patent, which was followed by Merlin Smith and Emanuel Stern’s 1967 patent outlining how best to produce the holes between layers. We now call these inter-layer holes through silicon vias (TSVs). Technology is still catching up to these 3-D concepts.
Three-dimensional integration offers exciting advantages. For example, the vertical distance between layers is much shorter than the horizontal dimensions across a chip. Three-dimensional circuits, therefore, operate faster and dissipate less power than their 2-D equivalent. A 3-D system is shockingly small, permitting it to fit much more conveniently into a tiny space. Think small portable electronics (e.g., credit cards).
But the most exciting advantage of 3-D integration isn’t the small form factor, higher speed, or lower power; it’s the natural ability to support many disparate technologies and functions as one integrated, heterogeneous system. Even better, each chip layer can be optimized for a particular function and technology, since the individual chips can each be developed in isolation. No more trading off different capabilities to combine disparate technologies on the same chip. Now we can use the absolute best technology for each layer and a completely different and optimized technology for a different layer. This approach enables all kinds of novel applications that until now couldn’t have been conceived or would have been cost-prohibitive.
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Imagine placing a microprocessor plane below a MEMS-accelerometer plane below an analog plane (with ADCs) below a temperature sensor, all below a video imager (which has to be at the top to “see”). All of these planes fit together into a tiny (smaller than a fingernail) silicon cube while operating at higher speeds and dissipating lower power.
There are technical issues, including: how to best make the TSVs, how to construct the system architecture to fully exploit the system’s 3-D nature, how to deliver power across these multiple planes, how to synchronize this system to best move data around the cube, how to manage system design complexity, and much more.
Two issues rise to the top. The first is power dissipation (specifically, power density). When many transistors switch at a high rate within a tiny volume, the temperature rises, which can impair performance and reliability. I believe this issue, albeit difficult, is technically solvable and simply will require a lot of good engineering.
The real problem is cost. How do we mature this technology quickly enough to drive the costs down to a point where volume commercial applications are possible? Many companies are close to producing tangible 3-D-based products. Cubes of highly dense memory will likely be the first serious and cost-effective product. Early versions are already available. Three-dimensional integration will soon be here in a serious way with what will be a fascinating assortment of all kinds of exciting new products. You won’t have to wait too long.
Eby G. Friedman is a Distinguished Professor in the Department of Electrical and Computer Engineering at the University of Rochester. Eby previously worked for Hughes Aircraft Company developing high-performance ICs for the US military. His current research and teaching interests include high-performance synchronous digital and mixed-signal nanoelectronic circuit design with application to high-speed portable processors and low-power wireless communications. Eby has written more than 400 papers, holds 12 patents, and is the author or editor of 16 books about the fields of high-speed and low-power CMOS design techniques, 3-D design methodologies, high-speed interconnect, and the theory and application of synchronous clock and power delivery. He is also a Senior Fulbright Fellow and an IEEE Fellow.
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