NAN: How long have you been at Michigan Technological University? What courses do you currently teach and what do you enjoy most about instructing?
SHIYAN: I have been with Michigan Tech for six years as an assistant professor. Effective September 2014, I will be an associate professor.
I have recently taught the graduate-level “Advanced Embedded System for Smart Infrastructure,” the graduate-level “Advanced Very-Large-Scale Integration (VLSI) Computer-Aided Design (CAD),” and the undergraduate-level “VLSI Design” courses.
The most exciting part about teaching is the interactions with students. For example, questions from students—although sometimes challenging—can be intriguing and it is fun to observe diversified thoughts. In addition, students taking graduate-level courses need to discuss their course projects with me. During the discussions, I can clearly see how excited they feel about their progress, which makes the teaching very enjoyable.
NAN: What “hot topics” currently interest your students?
SHIYAN: Students are very interested in embedded system designs for smart homes, including FPGA design and embedded programming for the scheduling of various smart home appliances to improve convenience and reduce the cost of electricity bills. I also frequently have meetings with students who are interested in portable or wearable electronics targeting health-care applications.
NAN: Describe your role as director of Michigan Tech’s VLSI CAD research lab.
SHIYAN: I have been advising a team of PhD and MS students who conduct research in the area of VLSI CAD in the Electrical and Computer Engineering (ECE) department. A main research focus of our lab is VLSI physical design including buffer insertion, layer assignment, routing, gate sizing, and so forth. In addition, we have developed some embedded system prototypes such as sensor-based video monitoring and a 3-D mouse (see Photos 1 and 2).
There is also growing collaboration between our lab and the power system lab on the research of a CAD technique for smart-grid systems. The collaboration has led to an innovative optimization technique for an automatic feeder remote terminal unit that addresses cybersecurity attacks to smart power distribution networks. Further, there is an ongoing joint project on an FPGA-based embedded system for power quality prediction.
Although most of my time as the research lab director is spent on student mentoring and project management, our lab also contributes considerably to education in our department. For example, instructional and lab materials for the undergraduate “VLSI Design” course are produced by our lab.
NAN: Tell us more about your smart home research and the technique you developed to address cybersecurity problems.
SHIYAN: My smart home research emphasizes embedded systems that handle scheduling and cybersecurity issues. Figure 1 shows a typical smart home system, which consists of various components such as household appliances, energy storage, photovoltaic (PV) arrays, and a plug-in hybrid electrical vehicle (PHEV) charger. Smart meters are installed at the customer side and connected to the smart power distribution system.
The smart meter can periodically receive updated pricing information from utility companies. The smart meter also has a scheduling unit that automatically determines the operation of each household appliance (e.g., the starting time and working power level), targeting the minimization of the monetary expense of each residential customer. This technology is called “smart home scheduling.”
In the real-time pricing model, utility pricing is determined by the load while the load is influenced by the pricing, forming a feedback loop. In this process, the pricing information is transmitted from the utility to the smart meters through some communication network, which could be wireless or wired. Cyber attackers can hack some access points in the transmission or just directly hack the smart meters. Those impacted smart meters would receive fake pricing information and generate the undesired scheduling solutions. Cyber attackers can take advantage of this by scheduling their own energy-consuming tasks during the inexpensive hours, which would be expensive without a cyber attack. This is an interesting topic I am working on.
NAN: Describe your VSLI research.
SHIYAN: Modern ICs and chips are ubiquitous. Their applications include smartphones, modern home appliances, PCs, and laptops, as well as the powerful servers for big data storage and processing. In VLSI and system-on-a-chip (SoC) design, the layout design (a.k.a., physical design) often involves billions of transistors and is therefore enormously complex. Handling such a complex problem requires high-performance software automation tools (i.e., physical design automation tools) to achieve design objectives within a reasonable time frame. VLSI physical design is a key part of my research area.
NAN: Are you involved in any other areas of research?
SHIYAN: I also work on microfluidic biochip design. The traditional clinical diagnosis procedure includes collecting blood from patients and then sending it to laboratories, which require space and are labor-intensive and expensive, yet sometimes inaccurate.
The invention of the lab on a chip (a.k.a., biochip) technology offers some relief. The expensive laboratory procedures can be simply performed within a small chip, which provides much higher sensitivity and detection accuracy in blood sample analysis and disease diagnosis. Some point-of-care versions of these have already become popular in the market.
A major weakness of the prevailing biochip technology is that such a chip often has very limited functionality in terms of the quantities it can measure. The reason is that currently only up to thousands of biochemical reactions can be handled in a single biochip. Since the prevailing biochips are always manually designed, this seems to be the best one can achieve. If a single biochip could simultaneously execute a few biological assays corresponding to related diseases, then the clinical diagnosis would be much less expensive and more convenient to conduct. This is also the case when utilizing biochips for biochemical research and drug discovery.
My aim for this biochip research project is to largely improve the integration complexity of miniaturized components in a biochip to provide many more functionalities. The growing design complexity has mandated a shift from the manual design process toward a CAD process.
Basically, in the microfluidic biochip CAD methodology, those miniaturized components, which correspond to fundamental biochemical operations (e.g., mix and split), are automatically placed and routed using computer algorithms. This methodology targets minimizing the overall completion time of all biochemical operations, limiting the sizes of biochips, and improving the yield in the biochip fabrication. In fact, some results from our work were recently featured on the front cover of IEEE Transactions on Nanobioscience (Volume 13, No. 1, 2014), a premier nanobioscience and engineering journal. In the future, we will consider inserting on-chip optical sensors to provide real-time monitoring of the biological assay execution, finding possible errors during execution, and dynamically reconfiguring the biochip for error recovery.
NAN: You’ve earned several distinctions and awards over the last few years. How do these acknowledgments help your research?
SHIYAN: Those awards and funding certainly help me a lot in pursuing the research of fascinating topics. For example, I am a 2014 recipient of the NSF CAREER award, which is widely regarded as one of the most prestigious honors for up-and-coming researchers in science and engineering.
My five-year NSF CAREER project will focus on carbon nanotube interconnect-based circuit design. In the prevailing 22-nm technology node, wires are made from coppers and such a thin copper wire has a very small cross-section area. This results in large wire resistance and large interconnect delay. In fact, the interconnect delay has become the limiting factor for chip timing. Due to the fundamental physical limits of copper wires, novel on-chip interconnect materials (e.g., carbon nanotubes and graphene nanoribbons) are more desirable due to their many salient features (e.g., superior conductivity and resilience to electromigration).
To judiciously integrate the benefits from both nanotechnology interconnects and copper interconnects, my NSF CAREER project will develop a groundbreaking physical layout codesign methodology for next-generation ICs. It will also develop various physical design automation techniques as well as a variation-aware codesign technique for the new methodology. This project aims to integrate the pioneering nanotechnologies into the practical circuit design and it has the potential to contribute to revolutionizing the prevailing circuit design paradigm.
NAN: Give us some background information. When did you first become interested in computer engineering?
SHIYAN: I started to work on computer engineering when I entered Texas A&M University conducting research with professor Jiang Hu, a leading expert in the field of VLSI physical design. I learned a lot about VLSI CAD from him and I did several interesting research projects including buffer insertion, gate sizing, design for manufacturability, and post silicon tuning. Through his introduction, I also got the chance to collaborate with leading experts from IBM Research on an important project called “slew buffering.”
NAN: Tell us more about your work at IBM Research.
SHIYAN: As VLSI technology scales beyond the 32-nm node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem.
Buffer insertion, which improves an IC’s timing performance by inserting non-inverting buffers or inverting buffers (a.k.a., inverters), has proven to be indispensable in interconnect optimization. It has been well documented that typically more than 25% of gates are buffers in IBM ASIC designs.
Together with my collaborators at IBM Research, I proposed a new slew buffering-driven dynamic programming technique. The testing with IBM ASIC designs demonstrated that our technique achieves a more than 100× speed increase compared to the classical buffering technique while still saving buffers. Therefore, the slew buffering-driven technique has been implemented and deployed into the IBM physical design flow as a default option.
IBM researchers have witnessed that the slew buffering technique contributes to a great reduction in the turnaround time of the physical synthesis flow. In addition, more extensive deployment of buffering techniques leads to superior design quality. Such an extensive buffer deployment-based interconnect synthesis was not possible prior to this work, due to the inefficiency of the previous buffering techniques.
After the publication of this work, various extensions to the slew buffering-driven technique were developed by other experts in the field. In summer 2010, I was invited by the group again to take a visiting professorship working on physical design, which resulted in a US patent being granted.
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