Editor's Letter Insights

A Tale of Two Green FPGA Contests

Written by Jeff Child

What is it about FPGA vendors and environmentally-themed design contests? I don’t know, except to say that it’s very cool and fun to follow! In the weeks of early July, as we wrapped up production of this issue of Circuit Cellar, one FPGA company was announcing the winners of its contest, while another was announcing the start of its new contest.

QuickLogic has revealed the winners of its “Challenge Climate Change” contest. Launched in November last year, the competition tasked participants to create a proof-of-concept of an intelligent IoT edge solution that addresses climate change. QuickLogic conducted the effort along with its subsidiary SensiML and implemented the contest via the Avnet Hackster.io online community.

Participates were directed to use the QuickLogic QuickFeather Development Kit and SensiML Analytics Toolkit to create a smart, low-power design running on the EOS S3 MCU + FPGA SoC (included on the QuickFeather development board). The projects were submitted to a highly qualified panel of judges for evaluation.

First place went to Pratyush Mallick for his project called “Forest Guardian”—a low-power solar-run device that detects illegal logging of forests at the IoT edge using acoustic data. Such devices aren’t new, but most solutions to date have relied on the cloud for postprocessing the data collected from sensors. Those are limited by network bandwidth and make for power-hungry devices. Pratyush’s proposed solar-powered device would be capable of classifying three classes of acoustic events: Normal (natural forest sound), Axe (logging of trees using an axe) and Chainsaw (logging of trees using a chainsaw). But the device would only send the classification results and device state over a radio frequency to the base station. The base station receives the data, uploads it to the cloud and generates an SMS text alert to the concerned authority if illegal logging is detected.

Second prize was awarded to Mithun Das for “Protect Peatlands for people and planet with help of SensiML”—a system that conserves peatlands by predicting early signs of drying, drought or fire using machine learning enabled by SensiML, Ubidots and the Helium network. And, the third prize went to Alejandro Sanchez for his “Illegal Logging Detector” project. Similar to the first prize winner’s project, this device combines SensiML and QuickFeather to detect chainsaw sounds and human voices in the forest.

Meanwhile, early July also saw the start of an FPGA contest, likewise environmentally themed. It’s been enough years since Intel acquired FPGA vendor Altera for us to get used to the notion of Intel as an FPGA player. And, even if its programmable logic business is just a portion of Intel’s portfolio, it remains among the top two FPGA companies (along with Xilinx). Intel’s new contest is called “InnovateFPGA.” Along with its contest co-sponsors—Terasic, Microsoft, Analog Devices, Arrow, Digi-Key, Mouser Electronics and Macnica—Intel is inviting ecologically minded teams to enter this design contest “to win cash prizes, medals and fame.”

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Competing teams will use the Terasic’s DE10-Nano FPGA Cloud Connectivity Kit with Analog Devices’ plug-in cards and IoT cloud connections provided by Microsoft Azure Cloud Services for the contest. The goal, according to Intel, is “to create design solutions that help to reduce the environmental impact and the demands that we place on the Earth’s resources.” All submitted projects must be based on, and make complete use of, the Intel Cyclone V SoC FPGA in the Cloud Connectivity Kit.

The Terasic DE10-Nano FPGA Cloud Connectivity Kit with an Analog Devices plug-in card and credits/limited-time access to Microsoft’s Azure Cloud Services will be provided at no cost to selected participating teams. Contest teams will demo their designs at regional finals and at the Grand Finale, to be held in San Jose, CA next year on June 23. Go to www.innovatefpga.com/portal for more information and to enter the InnovateFPGA contest. Deadline for technical proposals is September 30.

I love seeing advanced FPGA technologies in action, demonstrating ways to make the world better! Circuit Cellar will be following this one, and we’ll keep our eyes out for similar industry challenges.

PUBLISHED IN CIRCUIT CELLAR MAGAZINE• AUGUST 2021 #373 – Get a PDF of the issue

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Editor-in-Chief at Circuit Cellar | Website | + posts

Jeff Child has more than 28 years of experience in the technology magazine business—including editing and writing technical content, and engaging in all aspects of magazine leadership and production. He joined the Circuit Cellar after serving as Editor-in-Chief of COTS Journal for over 10 years. Over his career Jeff held senior editorial positions at several of leading electronic engineering publications, including EE Times and Electronic Design and RTC Magazine. Before entering the world of technology journalism, Jeff worked as a design engineer in the data acquisition market.

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A Tale of Two Green FPGA Contests

by Jeff Child time to read: 3 min