As I write this month’s column, it is a day after Intel released the 12th generation of its Core line of processors. Codenamed Adler Lake, these chips feature a new hybrid architecture. The hybrid scheme blends Intel’s “Performance-cores” (P-cores), the highest performing CPU core Intel has built, and “Efficient-cores” (E-cores), designed for scalable multi-threaded workload performance.
In the early years of my career (early 90s), a new Intel processor architecture was significant news for the embedded system market, but not “urgent” news. That’s because there used to be a significant gap of three years or so between when an Intel processor was released for the desktop/server computing market and when it became available for the broad embedded systems market.
That gap quickly shrank because makers of board-level embedded computers (SBCs), wanted the performance and functionality of the latest and greatest Intel chip as soon as possible. And Intel accommodated, and even went beyond and provided detailed roadmaps for their product lines so that embedded computing companies could plan ahead. Fast forward to today, and I’ve lost count of the number of board- and box-level embedded computing products we’ve seen based on the 11th-gen Intel Tiger Lake processor. That processor was released just over a year ago, in Fall 2020.
The Adler Lake hybrid processor architecture makes use of technology that ensures its two cores work smoothly together. According to Intel, the company’s Thread Director technology enables the two new core microarchitectures to work seamlessly together by guiding the operating system (OS) to place the right thread on the right core at the right time. Intel says it has worked with the company’s ecosystem on extensive testing to optimize performance and compatibility. It has published white papers for developers with guidance on how independent software vendors can optimize applications for performance hybrid platforms. Significantly, the hybrid architecture is the first built on the “Intel 7” process that enables scalable performance from 9W to 125W. Intel 7 was previously named “10nm SuperFin.”
An editor co-worker of mine some years ago remarked that Intel is really a systems company. Obviously, Intel’s revenue is all about chips, not systems, but that wasn’t what he meant. He meant by that Intel constantly enables the system infrastructure that its processors get designed into. You name it—everything from PCI to USB to PCI Express, Intel took a leadership role in developing the technology and the standards for every major computing interconnect scheme.
Along just those lines, the new Alder Lake processors lay claim to a number of firsts. They are the first processors in the industry to offer DDR5 memory for up to 4800MT/s. They are likewise the first processors to offer PCIe 5.0 (up to 16 lanes), which offers up to two-times the I/O throughput over PCIe 4.0, with up to an additional four lanes of PCIe 4.0 support. The devices provide up to 30MB of Intel Smart Cache (L3) and 14MB L2 cache for increased memory capacity with reduced latency. Furthermore, the new processors offer integrated high-speed wireless with “Intel Killer Wi-Fi 6E,” which combines Wi-Fi 6E connectivity with powerful gaming network technology to minimize lag, latency and packet loss.
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With the new 12th Gen Intel Core processors, Intel is launching the new Intel 600 Series chipset. New PCIe Gen 4.0 lanes make for 28 total lanes off the chipset, while integrated USB 3.2 Gen 2×2 provides up to double the bandwidth. Meanwhile, DMI Gen 4.0 increases the chipset-to-CPU throughput for fast access to peripheral devices and networking. As another first, Intel is bringing its Volume Management Device (VMD) to PC chipsets to simplify storage control by allowing direct control and management of NVMe-based SSDs from the PCIe bus without additional RAID controllers or other hardware adapters.
From Intel’s point of view, the new processor is a win for desktop and laptop PCs, particularly for gaming and video editing applications. But the history of Intel processors in the embedded market is sure to repeat. Over the next 12 months expect to see numerous board and box-level embedded computing products getting designed up and ready for your next system design.
PUBLISHED IN CIRCUIT CELLAR MAGAZINE• DECEMBER 2021 #377 – Get a PDF of the issue
Jeff served as Editor-in-Chief for both LinuxGizmos.com and its sister publication, Circuit Cellar magazine 6/2017—3/2022. In nearly three decades of covering the embedded electronics and computing industry, Jeff has also held senior editorial positions at EE Times, Computer Design, Electronic Design, Embedded Systems Development, and COTS Journal. His knowledge spans a broad range of electronics and computing topics, including CPUs, MCUs, memory, storage, graphics, power supplies, software development, and real-time OSes.
